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74ACT373

更新时间: 2024-10-01 22:56:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
10页 93K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

74ACT373 数据手册

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74ACT373  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUT NON INVERTING  
HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 5V  
LOW POWER DISSIPATION:  
ICC = 8 µA (MAX.) at TA = 25 oC  
COMPATIBLE WITH TTL OUTPUTS  
V
IH = 2V (MIN), V = 0.8V (MAX)  
IL  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL =24 mA (MIN)  
BALANCED PROPAGATION DELAYS:  
tPLH tPHL  
OPERATING VOLTAGE RANGE:  
B
M
(Plastic Package)  
(Micro Package)  
ORDER CODES :  
74ACT373B  
74ACT373M  
(OE).  
While the LE inputs is held at a high level, the Q  
outputs will follow the data input precisely or  
inversely. When the LE is taken low, the Q  
outputs will be latched precisely or inversely at  
the logic level of D input data. While the (OE)  
input is low, the 8 outputs will be in a normal logic  
state (high or low logic level) and while high level  
the outputs will be in a high impedance state.  
This device is designed to interface directly High  
Speed CMOS systems with TTL and NMOS  
components.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
VCC (OPR) = 4.5V to 5.5V  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 373  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The ACT373 is an advanced high-speed CMOS  
OCTAL D-TYPE LATCH with 3 STATE OUTPUT  
NON INVERTING fabricated with sub-micron  
silicon gate and double-layer metal wiring C2MOS  
technology. It is ideal for low power applications  
mantaining high speed operation similar to  
equivalentBipolar Schottky TTL.  
These 8 bit D-Type latch are controlled by a latch  
enable input (LE) and an output enable input  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/10  
April 1997  

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