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74ACT245T PDF预览

74ACT245T

更新时间: 2024-11-14 22:56:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 265K
描述
OCTAL BUS TRANSCEIVER 3-STATE

74ACT245T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.08
Is Samacsys:N控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:ACT
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:9 ns传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:4.4 mm
Base Number Matches:1

74ACT245T 数据手册

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74ACT245  
OCTAL BUS TRANSCEIVER  
WITH 3 STATE OUTPUTS (NON INVERTED)  
HIGH SPEED: t = 5.4ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4 µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS  
= 2V (MIN.), V = 0.8V (MAX.)  
50TRANSMISSION LINE DRIVING  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
ORDER CODES  
PACKAGE  
BALANCED PROPAGATION DELAYS:  
TUBE  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
DIP  
SOP  
74ACT245B  
74ACT245M  
V
CC  
74ACT245MTR  
74ACT245TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 245  
IMPROVED LATCH-UP IMMUNITY  
TSSOP  
The device is designed to interface directly High  
Speed CMOS systems with TTL, NMOS and  
CMOS output voltage levels.  
DESCRIPTION  
The 74ACT245 is an advanced high-speed CMOS  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
OCTAL  
BUS  
TRANSCEIVER  
(3-STATE)  
fabricated with sub-micron silicon gate and  
2
double-layer metal wiring C MOS tecnology.  
This IC is intended for two-way asynchronous  
communication between data buses and the  
direction of data transmission is determined by  
DIR input. The enable input G can be used to  
disable the device so that the buses are effectively  
isolated.  
IT IS PROHIBITED TO APPLY A SIGNAL TO A  
TERMINAL WHEN IT IS IN OUTPUT MODE AND  
WHEN A BUS THERMINAL IS FLOATING (HIGH  
IMPEDANCE STATE) IT IS REQUIRED TO FIX  
THE INPUT LEVEL BY MEANS OF EXTERNAL  
PULL DOWN OR PULL UP RESISTOR.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/9  

74ACT245T 替代型号

型号 品牌 替代类型 描述 数据表
MC74ACT245DTG ONSEMI

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