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74ACT241SJ PDF预览

74ACT241SJ

更新时间: 2024-11-13 22:56:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 105K
描述
Octal Buffer/Line Driver with 3-STATE Outputs

74ACT241SJ 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:5.30 MM, EIAJ TYPE2, SOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.13
Is Samacsys:N其他特性:OUTPUT ENABLE ACTIVE HIGH FOR ONE FUNCTION
控制类型:ENABLE LOW/HIGH系列:ACT
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.6 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:2.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

74ACT241SJ 数据手册

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November 1988  
Revised March 2005  
74AC241 74ACT241  
Octal Buffer/Line Driver with 3-STATE Outputs  
General Description  
Features  
The AC/ACT241 is an octal buffer and line driver designed  
to be employed as a memory address driver, clock driver  
and bus-oriented transmitter or receiver which provides  
improved PC board density.  
ICC and IOZ reduced by 50%  
Non-inverting 3-STATE outputs drive bus lines or buffer  
memory address registers  
Outputs source/sink 24 mA  
ACT241 has TTL-compatible inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC241SC  
74AC241SJ  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
74AC241MTC  
74AC241PC  
74ACT241SC  
74ACT241SJ  
74ACT241MTC  
74ACT241PC  
M20B  
M20D  
MTC20  
N20A  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OE1  
3-STATE Output Enable Input  
OE2  
3-STATE Output Enable Input (Active HIGH)  
I0I7  
O0O7  
Inputs  
Outputs  
Truth Tables  
Inputs  
Outputs  
OE1  
In  
(Pins 12, 14, 16, 18)  
L
L
L
H
X
L
H
Z
Connection Diagram  
H
Inputs  
Outputs  
OE2  
In  
(Pins 3, 5, 7, 9)  
H
H
L
L
H
X
L
H
Z
H
L
X
Z
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
High Impedance  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
DS009942  
www.fairchildsemi.com  

74ACT241SJ 替代型号

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