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74ACT18823SSC PDF预览

74ACT18823SSC

更新时间: 2024-11-10 22:14:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
6页 63K
描述
18-Bit D-Type Flip-Flop with 3-STATE Outputs

74ACT18823SSC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP56,.4
针数:56Reach Compliance Code:compliant
风险等级:5.73系列:ACT
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:18.415 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:90000000 Hz
最大I(ol):0.024 A湿度敏感等级:1
位数:9功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):9.5 ns
认证状态:Not Qualified座面最大高度:2.74 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.5 mm
Base Number Matches:1

74ACT18823SSC 数据手册

 浏览型号74ACT18823SSC的Datasheet PDF文件第2页浏览型号74ACT18823SSC的Datasheet PDF文件第3页浏览型号74ACT18823SSC的Datasheet PDF文件第4页浏览型号74ACT18823SSC的Datasheet PDF文件第5页浏览型号74ACT18823SSC的Datasheet PDF文件第6页 
August 1999  
Revised October 1999  
74ACT18823  
18-Bit D-Type Flip-Flop with 3-STATE Outputs  
General Description  
Features  
The ACT18823 contains eighteen non-inverting D-type flip-  
flops with 3-STATE outputs and is intended for bus oriented  
applications. The device is byte controlled. A buffered clock  
(CP), Clear (CLR), Clock Enable (EN) and Output Enable  
(OE) are common to each byte and can be shorted  
together for full 18-bit operation.  
Broadside pinout allows for easy board layout  
Separate control logic for each byte  
Extra data width for wider address/data paths or buses  
carrying parity  
Outputs source/sink 24 mA  
TTL-compatible inputs  
Ordering Code:  
Order Number  
74ACT18823SSC  
74ACT18823MTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Input (Active LOW)  
Clear (Active LOW)  
Clock Enable (Active LOW)  
Clock Pulse Input  
Inputs  
CLRn  
ENn  
CPn  
I0–I17  
O0–O17  
Outputs  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS500294  
www.fairchildsemi.com  

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