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74ACT16646DLRG4 PDF预览

74ACT16646DLRG4

更新时间: 2024-11-17 22:26:55
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件输入元件
页数 文件大小 规格书
12页 239K
描述
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

74ACT16646DLRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP, SSOP56,.4针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:4.82Is Samacsys:N
其他特性:DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIME DATA控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:ACT
JESD-30 代码:R-PDSO-G56JESD-609代码:e4
长度:18.41 mm负载电容(CL):50 pF
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP56,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:11.4 ns传播延迟(tpd):12.3 ns
认证状态:Not Qualified施密特触发器:No
座面最大高度:2.79 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
触发器类型:POSITIVE EDGE宽度:7.49 mm
Base Number Matches:1

74ACT16646DLRG4 数据手册

 浏览型号74ACT16646DLRG4的Datasheet PDF文件第2页浏览型号74ACT16646DLRG4的Datasheet PDF文件第3页浏览型号74ACT16646DLRG4的Datasheet PDF文件第4页浏览型号74ACT16646DLRG4的Datasheet PDF文件第5页浏览型号74ACT16646DLRG4的Datasheet PDF文件第6页浏览型号74ACT16646DLRG4的Datasheet PDF文件第7页 
54ACT16646, 74ACT16646  
16-BIT BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCAS127B – MARCH 1990 – REVISED APRIL 1996  
54ACT16646 . . . WD PACKAGE  
74ACT16646 . . . DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
Inputs Are TTL-Voltage Compatible  
Independent Registers for A and B Buses  
Multiplexed Real-Time and Stored Data  
1DIR  
1CLKAB  
1SAB  
GND  
1OE  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1CLKBA  
1SBA  
GND  
1B1  
2
3
Flow-Through Architecture Optimizes  
PCB Layout  
4
1A1  
5
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
1A2  
1B2  
6
V
V
7
CC  
CC  
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
8
9
500-mA Typical Latch-Up Immunity at  
125°C  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Packages Using  
25-mil Center-to-Center Pin Spacings and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Packages Using 25-mil Center-to-Center  
Pin Spacings  
description  
The ’ACT16646 are 16-bit bus transceivers  
consisting of D-type flip-flops and control circuitry  
with 3-state outputs arranged for multiplexed  
transmission of data directly from the data bus or  
from the internal storage registers. The devices  
can be used as two 8-bit transceivers or one 16-bit  
transceiver. Data on the A or B bus is clocked into  
the registers on the low-to-high transition of the  
appropriate clock (CLKAB or CLKBA) input.  
Figure 1 illustrates the four fundamental bus-  
management functions that can be performed  
with the bus transceivers and registers.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2SBA  
2CLKBA  
2OE  
2SAB  
2CLKAB  
2DIR  
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the  
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select  
controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for  
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between  
stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE  
high), A data may be stored in one register and/or B data may be stored in the other register.  
When an output function is disabled, the input function is still enabled and may be used to store and transmit  
data. Only one of the two buses, A or B, may be driven at a time.  
The 74ACT16646 is packaged in TI’s shrink small-outline package, which provides twice the functionality of  
standard small-outline packages in the same printed-circuit-board area.  
The 54ACT16646 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
74ACT16646 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74ACT16646DLRG4 替代型号

型号 品牌 替代类型 描述 数据表
74ACT16648DL TI

完全替代

16-BIT TRABSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
74ACT16646DL TI

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16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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