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74ACT16646

更新时间: 2024-11-17 23:00:15
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德州仪器 - TI 总线收发器输出元件
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描述
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

74ACT16646 数据手册

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54ACT16646, 74ACT16646  
16-BIT BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCAS127B – MARCH 1990 – REVISED APRIL 1996  
54ACT16646 . . . WD PACKAGE  
74ACT16646 . . . DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
Inputs Are TTL-Voltage Compatible  
Independent Registers for A and B Buses  
Multiplexed Real-Time and Stored Data  
1DIR  
1CLKAB  
1SAB  
GND  
1OE  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1CLKBA  
1SBA  
GND  
1B1  
2
3
Flow-Through Architecture Optimizes  
PCB Layout  
4
1A1  
5
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
1A2  
1B2  
6
V
V
7
CC  
CC  
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
8
9
500-mA Typical Latch-Up Immunity at  
125°C  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Packages Using  
25-mil Center-to-Center Pin Spacings and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Packages Using 25-mil Center-to-Center  
Pin Spacings  
description  
The ’ACT16646 are 16-bit bus transceivers  
consisting of D-type flip-flops and control circuitry  
with 3-state outputs arranged for multiplexed  
transmission of data directly from the data bus or  
from the internal storage registers. The devices  
can be used as two 8-bit transceivers or one 16-bit  
transceiver. Data on the A or B bus is clocked into  
the registers on the low-to-high transition of the  
appropriate clock (CLKAB or CLKBA) input.  
Figure 1 illustrates the four fundamental bus-  
management functions that can be performed  
with the bus transceivers and registers.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2SBA  
2CLKBA  
2OE  
2SAB  
2CLKAB  
2DIR  
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the  
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select  
controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for  
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between  
stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE  
high), A data may be stored in one register and/or B data may be stored in the other register.  
When an output function is disabled, the input function is still enabled and may be used to store and transmit  
data. Only one of the two buses, A or B, may be driven at a time.  
The 74ACT16646 is packaged in TI’s shrink small-outline package, which provides twice the functionality of  
standard small-outline packages in the same printed-circuit-board area.  
The 54ACT16646 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
74ACT16646 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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