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74ACT16543SSC PDF预览

74ACT16543SSC

更新时间: 2024-11-17 22:14:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 59K
描述
16-Bit Registered Transceiver with 3-STATE Outputs

74ACT16543SSC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP56,.4
针数:56Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.42
Is Samacsys:N控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:ACT
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:18.415 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:9 ns
传播延迟(tpd):9.8 ns认证状态:Not Qualified
座面最大高度:2.74 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:7.5 mmBase Number Matches:1

74ACT16543SSC 数据手册

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August 1999  
Revised October 1999  
74ACT16543  
16-Bit Registered Transceiver with 3-STATE Outputs  
General Description  
Features  
The ACT16543 contains sixteen non-inverting transceivers  
containing two sets of D-type registers for temporary stor-  
age of data flowing in either direction. Each byte has sepa-  
rate control inputs which can be shorted together for full  
16-bit operation. Separate Latch Enable and Output  
Enable inputs are provided for each register to permit inde-  
pendent input and output control in either direction of data  
flow.  
Independent registers for A and B buses  
Separate controls for data flow in each direction  
Back-to-back registers for storage  
Multiplexed real-time and stored data transfers  
Separate control logic for each byte  
Outputs source/sink 24 mA  
TTL-compatible inputs  
Ordering Code:  
Order Number  
74ACT16543SSC  
74ACT16543MTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
Pin Descriptions  
Pin Names  
Descriptions  
OEABn  
OEBAn  
CEABn  
CEBAn  
LEABn  
A-to-B Output Enable Input (Active LOW)  
B-to-A Output Enable Input (Active LOW)  
A-to-B Enable Input (Active LOW)  
B-to-A Enable Input (Active LOW)  
A-to-B Latch Enable Input (Active LOW)  
LEBAn  
A0–A15  
B-to-A Latch Enable Input (Active LOW)  
A-to-B Data Inputs or  
B-to-A 3-STATE Outputs  
B-to-A Data Inputs or  
B0–B15  
A-to-B 3-STATE Outputs  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS500301  
www.fairchildsemi.com  

74ACT16543SSC 替代型号

型号 品牌 替代类型 描述 数据表
74ACT16543SSCX FAIRCHILD

完全替代

Dual 8-bit Bus Transceiver
74ACTQ16543SSC FAIRCHILD

完全替代

16-Bit Registered Transceiver with 3-STATE Outputs

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