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74ACT16543

更新时间： 2024-11-17 23:00:15
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
10页 178K
描述
16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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74ACT16543 数据手册

 浏览型号74ACT16543的Datasheet PDF文件第2页浏览型号74ACT16543的Datasheet PDF文件第3页浏览型号74ACT16543的Datasheet PDF文件第4页浏览型号74ACT16543的Datasheet PDF文件第5页浏览型号74ACT16543的Datasheet PDF文件第6页浏览型号74ACT16543的Datasheet PDF文件第7页 
54ACT16543, 74ACT16543  
16-BIT REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCAS126B – MARCH 1990 – REVISED APRIL 1996  
54ACT16543 . . . WD PACKAGE  
74ACT16543 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
Inputs Are TTL-Voltage Compatible  
3-State True Outputs  
1OEAB  
1LEAB  
1CEAB  
GND  
1
2
3
4
5
6
7
8
9
56 1OEBA  
55 1LEBA  
54 1CEBA  
53 GND  
52 1B1  
Flow-Through Architecture Optimizes  
PCB Layout  
Distributed V  
and GND Pin  
CC  
1A1  
1A2  
Configurations Minimize High-Speed  
Switching Noise  
51 1B2  
V
50  
V
CC  
CC  
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
1A3  
1A4  
49 1B3  
48 1B4  
47 1B5  
46 GND  
45 1B6  
44 1B7  
43 1B8  
500-mA Typical Latch-Up Immunity at  
125°C  
1A5 10  
GND 11  
1A6 12  
1A7 13  
1A8 14  
Package Options Include Plastic Thin  
Shrink Small-Outline (DGG) and 300-mil  
Shrink Small-Outline (DL) Packages Using  
25-mil Center-to-Center Pin Spacings, and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Packages Using 25-mil Center-to-Center  
Pin Spacings  
15  
42  
2A1  
2B1  
2A2 16  
2A3 17  
41 2B2  
40 2B3  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GND  
2A4  
2A5  
2A6  
GND  
2B4  
2B5  
2B6  
description  
The ’ACT16543 are 16-bit registered transceivers  
that contain two sets of D-type latches for  
temporary storage of data flowing in either  
direction. The ’ACT16543 can be used as two  
8-bit transceivers or one 16-bit transceiver.  
Separate latch enable (LEAB or LEBA) and  
output-enable (OEAB or OEBA) inputs are  
provided for each register to permit independent  
control in either direction of data flow.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2CEAB  
2LEAB  
2OEAB  
2B7  
2B8  
GND  
2CEBA  
2LEBA  
2OEBA  
The A-to-B enable (CEAB) and OEAB inputs must  
be low to enter data from A or to output data to B.  
Having CEAB low and LEAB low makes the  
A-to-B latches transparent; a subsequent low-to-  
high transition at LEAB puts the A latches in the  
storage mode. Data flow from B to A is similar, but  
requires using the CEBA, LEBA, and OEBA  
inputs.  
The 74ACT16543 is packaged in TI’s shrink small-outline package, which provides twice the functionality of  
standard small-outline packages in the same printed-circuit-board area.  
The 54ACT16543 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
74ACT16543 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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