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74ACT16374TTR PDF预览

74ACT16374TTR

更新时间: 2024-10-26 05:05:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 279K
描述
16-BIT D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS (NON INVERTED)

74ACT16374TTR 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-48
针数:48Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.44
Is Samacsys:N系列:ACT
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:12.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:8.1 ns
传播延迟(tpd):13.2 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.1 mmBase Number Matches:1

74ACT16374TTR 数据手册

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74ACT16374  
16-BIT D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS (NON INVERTED)  
HIGH SPEED:  
= 120MHz (TYP.) at V = 5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 8µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS  
= 2V (MIN.), V = 0.8V (MAX.)  
V
IH  
IL  
TSSOP  
TUBE  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
T & R  
V
CC  
TSSOP  
74ACT16374TTR  
IMPROVED LATCH-UP IMMUNITY  
PIN CONNECTION  
DESCRIPTION  
The 74ACT16374 is an advanced high-speed  
CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)  
fabricated with sub-micron silicon gate and  
2
double-layer metal wiring C MOS tecnology.  
This 16 bit D-Type Flip-Flop is controlled by two  
clock inputs (CK) and two output enable inputs  
(OE). The device can be used as two 8-bit  
flip-flops or one 16-bit flip-flop.  
On the positive transition of the clock, the Q  
outputs will be set to the logic state that were  
setup at the D inputs.  
While the (OE) input is low, the outputs will be in  
a normal logic state (high or low logic level); while  
OE is high, the outputs will be in a high impedance  
state.  
The output control does not affect the internal  
operation of flip-flops; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
February 2003  
1/10  

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