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74ACT16240 PDF预览

74ACT16240

更新时间: 2024-01-17 21:19:01
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
7页 84K
描述
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs

74ACT16240 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SSOP包装说明:0.300 INCH, MO-118, SSOP-48
针数:48Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.41
Is Samacsys:N控制类型:ENABLE LOW
系列:ACTJESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:15.875 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:4
功能数量:4端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:7.8 ns
传播延迟(tpd):7.8 ns认证状态:Not Qualified
座面最大高度:2.74 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

74ACT16240 数据手册

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August 1999  
Revised October 1999  
74ACT16240  
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs  
General Description  
Features  
The ACT16240 contains sixteen inverting buffers with 3-  
STATE outputs designed to be employed as a memory and  
address driver, clock driver, or bus-oriented transmitter/  
receiver. The device is nibble controlled. Each nibble has  
separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
Separate control logic for each byte  
16-bit version of the ACT240  
Outputs source/sink 24 mA  
TTL-compatible inputs  
Ordering Code:  
Order Number  
74ACT16240SSC  
74ACT16240MTD  
Package Number  
MS48A  
Package Description  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD48  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Inputs (Active LOW)  
I0–I15  
O0–O15  
Inputs  
Outputs  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS500293  
www.fairchildsemi.com  

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