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74ACT14DCQR

更新时间: 2024-11-28 13:04:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 133K
描述
Inverter, ACT Series, 6-Func, 1-Input, CMOS, CDIP14, CERAMIC, DIP-14

74ACT14DCQR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.32
系列:ACTJESD-30 代码:R-GDIP-T14
JESD-609代码:e0长度:19.43 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
最大I(ol):0.024 A功能数量:6
输入次数:1端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
施密特触发器:YES座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

74ACT14DCQR 数据手册

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November 1988  
Revised September 2005  
74AC14 • 74ACT14  
Hex Inverter with Schmitt Trigger Input  
General Description  
Features  
The 74AC14 and 74ACT14 contain six inverter gates each with  
a Schmitt trigger input. They are capable of transforming slowly  
changing input signals into sharply defined, jitter-free output sig-  
nals. In addition, they have a greater noise margin than conven-  
tional inverters.  
I
reduced by 50%  
CC  
Outputs source/sink 24 mA  
74ACT14 has TTL-compatible inputs  
The 74AC14 and 74ACT14 have hysteresis between the posi-  
tive-going and negative-going input thresholds (typically 1.0V)  
which is determined internally by transistor ratios and is essen-  
tially insensitive to temperature and supply voltage variations.  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74AC14SC  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74AC14SCX_NL  
(Note 1)  
M14A  
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74AC14SJ  
M14D  
MTC14  
MTC14  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74AC14MTC  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74AC14MTCX_NL  
(Note 1)  
74AC14PC  
N14A  
M14A  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
74ACT14SC  
74ACT14MTC  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
MTC14  
MTC14  
74ACT14MTCX_NL  
(Note 1)  
74ACT14PC  
N14A  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
DS009917  
www.fairchildsemi.com  

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