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74ACT138 PDF预览

74ACT138

更新时间: 2024-11-24 23:00:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
10页 280K
描述
3 TO 8 LINE DECODER (INVERTING)

74ACT138 数据手册

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74ACT138  
3 TO 8 LINE DECODER (INVERTING)  
HIGH SPEED: t = 5ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS  
= 2V (MIN.), V = 0.8V (MAX.)  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
DIP  
SOP  
74ACT138B  
74ACT138M  
V
CC  
74ACT138MTR  
74ACT138TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 138  
IMPROVED LATCH-UP IMMUNITY  
TSSOP  
Three enable inputs are provided to ease cascade  
connection and application of address decoders  
for memory systems.  
The device is designed to interface directly High  
Speed CMOS systems with TTL, NMOS and  
CMOS output voltage levels.  
DESCRIPTION  
The 74ACT138 is an advanced high-speed CMOS  
3 TO 8 LINE DECODER (INVERTING) fabricated  
with sub-micron silicon gate and double-layer  
2
metal wiring C MOS tecnology.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
If the device is enabled, 3 binary select inputs (A,  
B, and C) determine which one of the outputs will  
go low. If enable input G1 is held low or either G2A  
or G2B is held high, the decoding function is  
inhibited and all the 8 outputs go to high.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/10  

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