June 1996
Revised November 1999
74ACT1284
IEEE 1284 Transceiver
General Description
Features
The 74ACT1284 contains four non-inverting bidirectional
buffers and three non-inverting buffers with open Drain out-
puts and high drive capability on the B Ports. It is intended
to provide a standard signaling method for a bi-direction
parallel peripheral in an Extended Capabilities Port mode
(ECP).
■ TTL-compatible inputs
■ A Ports have standard 4 mA totem pole outputs
■ Typical input hysteresis of 0.5V
■ B Port high drive source/sink capability of 14 mA
■ Bidirectional non-inverting buffers
■ Supports IEEE P1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
The HD (active HIGH) input pin enables the B Ports to
switch from open Drain to a high drive totem pole output,
capable of sourcing 14 mA on all seven buffers. The DIR
input determines the direction of data flow on the bidirec-
tional buffers. DIR (active HIGH) enables data flow from A
Ports to B Ports. DIR (active LOW) enables data flow from
B Ports to A Ports.
■ B Port outputs in High Impedance mode during power
down
■ Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number Package Number
Package Description
74ACT1284SC
74ACT1284MSA
74ACT1284MTC
M20B
MSA20
MTC20
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
HD
High Drive Enable input (Active HIGH)
Direction Control Input
Side A Inputs or Outputs
Side B Inputs or Outputs
Side A Inputs
DIR
A
B
A
1 - A4
1 - B4
5 - A7
B5 - B7
Side B Outputs
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© 1999 Fairchild Semiconductor Corporation
DS011683
www.fairchildsemi.com