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74ACT11656DWR PDF预览

74ACT11656DWR

更新时间: 2024-01-08 10:11:00
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件电机
页数 文件大小 规格书
11页 253K
描述
ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO28, PLASTIC, SOIC-28

74ACT11656DWR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP28,.3Reach Compliance Code:unknown
风险等级:5.92控制类型:ENABLE LOW
JESD-30 代码:R-PDIP-T28JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:8
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP28,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
认证状态:Not Qualified子类别:Bus Driver/Transceivers
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

74ACT11656DWR 数据手册

 浏览型号74ACT11656DWR的Datasheet PDF文件第2页浏览型号74ACT11656DWR的Datasheet PDF文件第3页浏览型号74ACT11656DWR的Datasheet PDF文件第4页浏览型号74ACT11656DWR的Datasheet PDF文件第5页浏览型号74ACT11656DWR的Datasheet PDF文件第6页浏览型号74ACT11656DWR的Datasheet PDF文件第7页 
ꢀ ꢁ ꢂꢃ ꢄꢅꢅꢆ ꢇꢆ  
ꢈ ꢃꢄꢂꢉ ꢊꢋꢌ ꢌ ꢍꢎꢏ ꢉ ꢐꢑ ꢍ ꢒ ꢎꢐ ꢓ ꢍꢎ  
ꢔ ꢐ ꢄꢕ ꢖꢂꢎꢐ ꢄ ꢗ ꢃꢕꢍ ꢃꢘꢍꢎ ꢏꢙ ꢍꢑꢍ ꢎꢂꢄꢈ ꢎ ꢂꢑꢒ ꢚ ꢛꢜꢄꢂꢄ ꢍ ꢈ ꢋꢄ ꢖ ꢋꢄꢜ  
SCAS460A − DECEMBER 1994 − REVISED APRIL 1996  
DW PACKAGE  
(TOP VIEW)  
D
D
Inputs Are TTL-Voltage Compatible  
Combines 244 and 280 Functions In  
One Package  
Y1  
Y2  
OE1  
OE2  
OE3  
A1  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
D
D
D
D
Flow-Through Architecture Optimizes  
PCB Layout  
2
Y3  
3
Center-Pin V  
Minimize High-Speed Switching Noise  
and GND Configurations  
Y4  
4
CC  
Y5  
A2  
5
GND  
GND  
GND  
GND  
Y6  
A3  
6
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
500-mA Typical Latch-Up Immunity at  
V
7
CC  
V
8
CC  
A4  
A5  
A6  
9
125°C  
10  
11  
Y7  
description  
Y8 12  
ΣE 13  
ΣO 14  
17 A7  
16 A8  
15 PI  
The 74ACT11656 contains eight noninverting  
buffers with 3-state outputs and a 9-bit parity  
generator/checker. The device is intended for  
bus-oriented applications.  
When data is transmitted, the parity input (PI) terminal is configured as an input and combined with the A-input  
data to generate a flag on either parity output (ΣE or ΣO) terminal, depending on the number of inputs that are  
high.  
The output-enable (OE1, OE2, and OE3) inputs can be used to disable the device so that the buses are  
effectively isolated.  
The 74ACT11656 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLES  
INPUTS  
OUTPUT  
Y
OE1  
L
OE2  
L
OE3  
L
A
L
L
H
Z
Z
Z
L
L
L
H
X
X
X
H
X
X
X
H
X
X
X
H
PARITY  
OUTPUTS  
NO. OF INPUTS HIGH  
(PI, A1−A8)  
ΣO  
L
ΣE  
H
L
EVEN 0, 2, 4, 6, 8  
ODD 1, 3, 5, 7, 9  
Any OE = high  
H
Z
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢄꢨ  
Copyright 1996, Texas Instruments Incorporated  
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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