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74ACT11238_10 PDF预览

74ACT11238_10

更新时间: 2022-10-12 16:15:24
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德州仪器 - TI /
页数 文件大小 规格书
7页 96K
描述
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

74ACT11238_10 数据手册

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74ACT11238  
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER  
SCAS054 – NOVEMBER 1988 – REVISED APRIL 1993  
D OR N PACKAGE  
(TOP VIEW)  
Designed Specifically for High-Speed  
Memory Decoders and Data Transmission  
Systems  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Y0  
A
B
Y1  
Y2  
Y3  
GND  
Y4  
Y5  
Noninverting Version of ACT11138  
Incorporates 3 Enable Inputs to Simplify  
Cascading and/or Data Reception  
C
V
Inputs Are TTL-Voltage Compatible  
CC  
G1  
G2A  
G2B  
Flow-Through Architecture Optimizes  
Y6  
Y7  
PCB Layout  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
500-mA Typical Latch-Up Immunity  
at 125°C  
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
description  
The 74ACT11238 circuit is designed to be used in high-performance memory-decoding or data-routing  
applications requiring very short propagation delay times. In high-performance memory systems, this decoder  
can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing  
a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than  
the typical access time of the memory. This means that the effective system delay introduced by the decoder  
is negligible.  
The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two  
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.  
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one  
inverter. An enable input can be used as a data input for demultiplexing applications.  
The 74ACT11238 is characterized for operation from – 40°C to 85°C.  
FUNCTION TABLE  
ENABLE  
INPUTS  
SELECT  
INPUTS  
OUTPUTS  
G1  
X
G2A  
H
X
X
L
G2B  
X
H
X
L
C
X
X
X
L
B
X
X
X
L
A
X
X
X
L
Y0  
L
Y1  
L
Y2  
L
Y3  
L
Y4  
L
Y5  
L
Y6  
L
Y7  
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
H
H
H
H
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
H
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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