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74ACT11194DWR PDF预览

74ACT11194DWR

更新时间： 2024-01-03 18:45:45
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
55页 578K
描述
ACT SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20, PLASTIC, SO-20

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74ACT11194DWR 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84其他特性：HOLD MODE; CENTER VCC/GND PINS
计数方向：BIDIRECTIONAL系列：ACT
JESD-30 代码：R-PDIP-T20逻辑集成电路类型：PARALLEL IN PARALLEL OUT
位数：4功能数量：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：8.3 ns
认证状态：Not Qualified最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子位置：DUAL触发器类型：POSITIVE EDGE
最小 fmax：130 MHzBase Number Matches：1

74ACT11194DWR 数据手册

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SCAS094 − NOVEMBER 1989 − REVISED APRIL 1993  
DW OR N PACKAGE  
(TOP VIEW)  
• Inputs Are TTL-Voltage Compatible  
• Parallel-to-Serial, Serial-to-Parallel  
Conversions  
SR SER  
S0  
S1  
A
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
• Left or Right Shifts  
Q
Q
A
B
• Parallel Synchronous Loading  
• Direct Overriding Clear  
GND  
GND  
GND  
GND  
B
V
V
CC  
CC  
• Temporary Data Latching Capability  
• Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
C
Q
Q
D
CLR  
CLK  
C
D
• EPICt (Enhanced-Performance Implanted  
CMOS) 1-mm Process  
SL SER  
• 500-mA Typical Latch-Up Immunity  
at 125°C  
• Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
description  
This bidirectional shift register features parallel outputs, right-shift and left-shift serial inputs,  
operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of  
operation, namely:  
Parallel (broadside) load  
Shift right (in the direction Q toward Q )  
A
D
Shift left (in the direction Q toward Q )  
D
A
Inhibit clocking (do nothing).  
Synchronous parallel loading is accomplished by applying the 4 bits of data and taking both mode control inputs,  
S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive  
transition of the clock input. During loading, serial data flow is inhibited.  
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.  
Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left  
synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when  
both mode control inputs are low.  
The 74ACT11194 is characterized for operation from − 40°C to 85°C.  
EPIC is a trademark of Texas Instruments Incorporated.  
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Copyright 1993, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
1234567...55

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