54ACT11010, 74ACT11010
TRIPLE 3-INPUT POSITIVE-NAND GATES
SCAS018A – D2957, JULY 1987 – REVISED APRIL 1993
54ACT11010 . . . J PACKAGE
74ACT11010 . . . D OR N PACKAGE
• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture to Optimize
(TOP VIEW)
PCB Layout
• Center-Pin V
and GND Configurations
Minimize High-Speed Switching Noise
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
2Y
GND
GND
3Y
1B
1C
2A
• EPIC (Enhanced-Performance Implanted
CMOS) 1- m Process
V
V
CC
CC
• 500-mA Typical Latch-Up Immunity
at 125°C
2B
2C
3A
3C
3B
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
54ACT11010 . . . FK PACKAGE
(TOP VIEW)
description
These devices contain three independent 3-input
NAND gates. They perform the Boolean functions
Y = A B C or Y = A + B + C in positive logic.
3
2
1
20 19
18
2C
3A
NC
3B
3C
1C
1B
NC
1A
1Y
4
5
6
7
8
The 54ACT11010 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The 74ACT11010 is characterized for
operation from – 40°C to 85°C.
17
16
15
14
9 10 11 12 13
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
H
L
B
H
X
L
C
H
X
X
L
NC – No internal connection
L
H
H
H
logic diagram (positive logic)
X
X
1
X
1A
2
16
15
1B
1Y
1C
†
logic symbol
14
11
10
2A
2B
2C
1
1A
16
1B
15
1C
14
2A
11
3
6
&
2Y
3Y
2
3
6
1Y
2Y
3Y
9
8
7
3A
3B
3C
2B
10
2C
9
3A
8
3B
7
3C
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
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