Datasheet > 74ACT10TTR

74ACT10TTR

更新时间： 2024-11-26 23:24:03

品牌	Logo	应用领域
其他 - ETC		触发器逻辑集成电路光电二极管栅
页数	文件大小	规格书
8页	61K
描述
Triple 3-input NAND Gate

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中文翻译

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数据手册

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74ACT10TTR 数据手册

74ACT10

TRIPLE 3-INPUT NAND GATE

■

HIGH SPEED: t = 4.5ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 4µA(MAX.) at T =25°C

■

COMPATIBLE WITH TTL OUTPUTS

= 2V (MIN.), V = 0.8V (MAX.)

50Ω TRANSMISSION LINE DRIVING

DIP

SOP

TSSOP

T & R

CAPABILITY

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 24mA (MIN)

BALANCED PROPAGATION DELAYS:

ORDER CODES

PACKAGE

PLH

PHL

TUBE

OPERATING VOLTAGE RANGE:

(OPR) = 4.5V to 5.5V

DIP

SOP

74ACT10B

74ACT10M

74ACT10MTR

74ACT10TTR

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 10

IMPROVED LATCH-UP IMMUNITY

TSSOP

The device is designed to interface directly High

Speed CMOS systems with TTL, NMOS and

CMOS output voltage levels.

All inputs and outputs are equipped with protec-

tion circuits against static discharge, giving them

2KV ESD immunity and transient excess voltage.

DESCRIPTION

The 74ACT10 is an advanced high-speed CMOS

TRIPLE 3-INPUT NAND GATE fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS tecnology.

The internal circuit is composed of 3 stages

including buffer output, which enables high noise

immunity and stable output.

PIN CONNECTION AND IEC LOGIC SYMBOLS

April 2001

1/8

12 3 4 5 6 7 8

中文翻译

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