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74ACQ646SDCQR PDF预览

74ACQ646SDCQR

更新时间: 2024-01-04 11:55:06
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路
页数 文件大小 规格书
12页 213K
描述
AC SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24, 0.300 INCH, SLIM, CERAMIC, DIP-24

74ACQ646SDCQR 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.71Is Samacsys:N
系列:ACJESD-30 代码:R-GDIP-T24
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):14 ns
认证状态:Not Qualified座面最大高度:5.715 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

74ACQ646SDCQR 数据手册

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March 1993  
74ACQ646 54ACTQ/74ACTQ646  
#
Quiet Series Octal Transceiver/Register  
with TRI-STATE Outputs  
É
General Description  
Features  
Y
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
The ’ACQ/’ACTQ646 consist of registered bus transceiver  
circuits, with outputs, D-type flip-flops, and control circuitry  
providing multiplexed transmission of data directly from the  
input bus or from the internal storage registers. Data on the  
A or B bus will be loaded into the respective registers on the  
LOW-to-HIGH transition of the appropriate clock pin (CPAB  
or CPBA). The four fundamental handling functions avail-  
able are illustrated in Figures 1–4.  
Y
Y
Y
Y
Y
Y
Y
Y
Guaranteed pin-to-pin skew AC performance  
Independent registers for A and B busses  
Multiplexed real-time and stored data transfers  
300 mil slim dual-in-line package  
Outputs source/sink 24 mA  
Faster prop delays than the standard ’AC/’ACT646  
4 kV minimum ESD immunity  
The ’ACQ/’ACTQ utilizes NSC Quiet Series technology to  
guarantee quiet output switching and improved dynamic  
threshold performance. FACT Quiet SeriesTM features  
GTOTM output control and undershoot corrector in addition  
to a split ground bus for superior performance.  
Standard Military Drawing (SMD)  
Ð ’ACTQ646: 5962-92196  
Logic Symbols  
Connection Diagrams  
Pin Assignment  
for DIP, Flatpak and SOIC  
IEEE/IEC  
TL/F/10635–1  
Pin Names  
Description  
TL/F/10635–3  
A A  
0
Data Register A Inputs  
Data Register A Outputs  
Data Register B Inputs  
Data Register B Outputs  
7
Pin Assignment  
for LCC  
B B  
0
7
CPAB, CPBA Clock Pulse Inputs  
SAB, SBA  
Transmit/Receive Inputs  
TL/F/10635–2  
G
Output Enable Input  
DIR  
Direction Control Input  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
FACTTM, FACT Quiet SeriesTM and GTOTM are trademarks of National Semiconductor Corporation.  
TL/F/10635–4  
C
1995 National Semiconductor Corporation  
TL/F/10635  
RRD-B30M75/Printed in U. S. A.  

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