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74AC899QCX PDF预览

74AC899QCX

更新时间: 2024-02-21 15:23:44
品牌 Logo 应用领域
美国国家半导体 - NSC 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
14页 207K
描述
9-Bit Latchable Transceiver with Parity Generator/Checker

74AC899QCX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.024 A
位数:8功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
包装方法:TAPE AND REEL电源:3.3/5 V
Prop。Delay @ Nom-Sup:15.5 ns认证状态:Not Qualified
子类别:Bus Driver/Transceivers表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
Base Number Matches:1

74AC899QCX 数据手册

 浏览型号74AC899QCX的Datasheet PDF文件第2页浏览型号74AC899QCX的Datasheet PDF文件第3页浏览型号74AC899QCX的Datasheet PDF文件第4页浏览型号74AC899QCX的Datasheet PDF文件第5页浏览型号74AC899QCX的Datasheet PDF文件第6页浏览型号74AC899QCX的Datasheet PDF文件第7页 
August 1994  
74AC899 54ACT/74ACT899  
#
9-Bit Latchable Transceiver  
with Parity Generator/Checker  
General Description  
Features  
Y
Latchable transceiver with output sink of 24 mA  
The ’AC/’ACT899 is a 9-bit to 9-bit parity transceiver with  
transparent latches. The device can operate as a feed-  
through transceiver or it can generate/check parity from the  
8-bit data busses in either direction. The ’AC/’ACT899 fea-  
tures independent latch enables for the A-to-B direction and  
the B-to-A direction, a select pin for ODD/EVEN parity, and  
separate error signal output pins for checking parity.  
Y
Option to select generate parity and check or ‘‘feed-  
through’’ data/parity in directions A-to-B or B-to-A  
Independent latch enable for A-to-B and B-to-A direc-  
tions  
Y
Y
Y
Y
Y
Y
Select pin for ODD/EVEN parity  
ERRA and ERRB output pins for parity checking  
Ability to simultaneously generate and check parity  
May be used in system applications in place of the ’280  
May be used in system applications in place of the ’657  
and ’373 (no need to change T/R to check parity)  
4 kV minimum ESD immunity  
Y
Logic Symbol  
Connection Diagram  
Pin Assignment for PCC and LCC  
TL/F/10637–1  
TL/F/10637–2  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
FACTTM is a trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/10637  
RRD-B30M75/Printed in U. S. A.  

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