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74AC648SCQR

更新时间: 2024-01-01 12:06:33
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 75K
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74AC648SCQR 数据手册

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November 1988  
Revised August 2000  
74AC648  
Octal Transceiver/Register with 3-STATE Outputs  
General Description  
Features  
Independent registers for A and B buses  
Multiplexed real-time and stored data transfers  
3-STATE outputs  
The AC648 consists of registered bus transceiver circuits,  
with outputs, D-type flip-flops and control circuitry providing  
multiplexed transmission of data directly from the input bus  
or from the internal storage registers. Data on the A or B  
bus will be loaded into the respective registers on the  
LOW-to-HIGH transition of the appropriate clock pin (CPAB  
or CPBA). The four fundamental data handling functions  
available are illustrated in Figure 1, Figure 2, Figure 3, and  
Figure 4.  
300 mil slim dual-in-line package  
Outputs source/sink 24 mA  
Inverted data to output  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC648SC  
M24B  
N24C  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
74AC648SPC  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
A0A7  
B0B7  
Data Register A Inputs,  
Data Register A 3-STATE Outputs  
Data Register B Inputs,  
Data Register B 3-STATE Outputs  
Clock Pulse Inputs  
CPAB, CPBA  
SAB, SBA  
DIR, G  
Transmit/Receive Inputs  
Output Enable Inputs  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2000 Fairchild Semiconductor Corporation  
DS010133  
www.fairchildsemi.com  

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