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74AC646_00

更新时间: 2024-09-27 04:28:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
9页 82K
描述
Octal Transceiver/Register with 3-STATE Outputs

74AC646_00 数据手册

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November 1988  
Revised October 2000  
74AC646 74ACT646  
Octal Transceiver/Register with 3-STATE Outputs  
General Description  
Features  
Independent registers for A and B buses  
Multiplexed real-time and stored data transfers  
3-STATE outputs  
The AC/ACT646 consist of registered bus transceiver cir-  
cuits, with outputs, D-type flip-flops and control circuitry  
providing multiplexed transmission of data directly from the  
input bus or from the internal storage registers. Data on the  
A or B bus will be loaded into the respective registers on  
the LOW-to-HIGH transition of the appropriate clock pin  
(CPAB or CPBA). The four fundamental data handling  
functions available are illustrated in Figures 1, 2, 3, and  
Figure 4.  
300 mil dual-in-line package  
Outputs source/sink 24 mA  
ACT646 has TTL compatible inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC646SC  
M24B  
N24C  
M24B  
N24C  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
74AC646SPC  
74ACT646SC  
74ACT646SPC  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
A0A7  
B0B7  
Data Register A Inputs  
Data Register A Outputs  
Data Register B Inputs  
Data Register B Outputs  
Clock Pulse Inputs  
CPAB, CPBA  
SAB, SBA  
G
Transmit/Receive Inputs  
Output Enable Input  
DIR  
Direction Control Input  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2000 Fairchild Semiconductor Corporation  
DS010132  
www.fairchildsemi.com  

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