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74AC574 PDF预览

74AC574

更新时间: 2024-01-02 06:10:10
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器输出元件
页数 文件大小 规格书
11页 83K
描述
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING

74AC574 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP20,.25
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.15
Is Samacsys:N系列:AC
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:60000000 Hz
最大I(ol):0.012 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 V传播延迟(tpd):16.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
Base Number Matches:1

74AC574 数据手册

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74AC574  
OCTAL D-TYPE FLIP FLOP  
WITH 3 STATE OUTPUT NON INVERTING  
HIGH SPEED:  
fMAX =220MHz(TYP.) at VCC =5V  
LOW POWER DISSIPATION:  
ICC =8 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
VNIH = VNIL =28% VCC (MIN.)  
50TRANSMISSIONLINEDRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 24 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
DIP  
SOP  
TSSOP  
ORDER CODES  
TUBE  
PACKAGE  
DIP  
T & R  
M74AC574B  
M74AC574M  
SOP  
M74AC574MTR  
M74AC574TTR  
TSSOP  
OPERATING VOLTAGERANGE:  
outputs will be set to logic state that were setup  
at the D inputs.  
While the (OE) input is low, the 8 outputs will be  
in a normal logic state (high or low logic level)  
and while high level the outputs will be in a high  
impedance state.  
VCC (OPR)= 2V to 6V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES574  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The AC574 is an advanced high-speed CMOS  
OCTAL D-TYPE FLIP FLOP with 3 STATE  
OUTPUT NON INVERTING fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
These 8 bit D-Type flip-flops are controlled by a  
clock input (CK)and an output enable input (OE).  
On the positive transition of the clock, the Q  
The output control does not affect the internal  
operation of flip flop; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/11  
February 2000  

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