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74AC573PC PDF预览

74AC573PC

更新时间: 2024-11-18 22:53:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 91K
描述
Octal Latch with 3-STATE Outputs

74AC573PC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.13
其他特性:BROADSIDE VERSION OF 373系列:AC
JESD-30 代码:R-PDIP-T20长度:26.075 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.012 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:RAIL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 VProp。Delay @ Nom-Sup:11 ns
传播延迟(tpd):12.5 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

74AC573PC 数据手册

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November 1988  
Revised October 1999  
74AC573 • 74ACT573  
Octal Latch with 3-STATE Outputs  
General Description  
The 74AC573 and 74ACT573 are high-speed octal latches  
with buffered common Latch Enable (LE) and buffered  
common Output Enable (OE) inputs.  
Features  
ICC and IOZ reduced by 50%  
Inputs and outputs on opposite sides of package allow-  
ing easy interface with microprocessors  
The 74AC573 and 74ACT573 are functionally identical to  
the 74AC373 and 74ACT373 but with inputs and outputs  
on opposite sides.  
Useful as input or output port for microprocessors  
Functionally identical to 74AC373 and 74ACT373  
3-STATE outputs for bus interfacing  
Outputs source/sink 24 mA  
74ACT573 has TTL-compatible inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC573SC  
74AC573SJ  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74AC573MTC  
74AC573PC  
74ACT573SC  
74ACT573SJ  
74ACT573MTC  
74ACT573PC  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20B  
M20D  
MTC20  
N20A  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
Data Inputs  
Latch Enable Input  
D0–D7  
LE  
OE  
3-STATE Output Enable Input  
3-STATE Latch Outputs  
O0–O7  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS009973  
www.fairchildsemi.com  

74AC573PC 替代型号

型号 品牌 替代类型 描述 数据表
74ACQ573PC FAIRCHILD

类似代替

Quiet Series⑩ Octal Latch with 3-STATE Output
CD74AC573E TI

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Octor Transparent Latch, 3-state
SN74AC573N TI

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