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74AC573MTR PDF预览

74AC573MTR

更新时间: 2024-11-10 00:00:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
12页 167K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

74AC573MTR 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.12
Is Samacsys:N其他特性:BROADSIDE VERSION OF 373
系列:ACJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.012 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3/5 V
Prop。Delay @ Nom-Sup:16.5 ns传播延迟(tpd):16.5 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

74AC573MTR 数据手册

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74AC573  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUTS (NON INVERTED)  
HIGH SPEED: t = 4.5ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4µA(MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
50TRANSMISSION LINE DRIVING  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
ORDER CODES  
PACKAGE  
BALANCED PROPAGATION DELAYS:  
t
t
TUBE  
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
DIP  
SOP  
74AC573B  
74AC573M  
V
CC  
74AC573MTR  
74AC573TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 573  
IMPROVED LATCH-UP IMMUNITY  
TSSOP  
outputs will follow the data input precisely.  
When the LE is taken low, the Q outputs will be  
latched at the logic level of D input data. While the  
(OE) input is low, the 8 outputs will be in a normal  
logic state (high or low logic level); while OE is in  
high level, the outputs will be in a high impedance  
state.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74AC573 is an advanced high-speed CMOS  
OCTAL D-TYPE LATCH with 3 STATE OUTPUTS  
NON INVERTING fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
technology.  
These 8 bit D-Type latch are controlled by a latch  
enable input (LE) and an output enable input (OE).  
While the LE inputs is held at a high level, the Q  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/11  

74AC573MTR 替代型号

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