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74AC573MTC_NL PDF预览

74AC573MTC_NL

更新时间: 2024-11-17 13:04:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
10页 91K
描述
Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 4.40 MM, LEAD FREE, MO-153AC, TSSOP-20

74AC573MTC_NL 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:unknown风险等级:5.65
Is Samacsys:N其他特性:BROADSIDE VERSION OF 373
系列:ACJESD-30 代码:R-PDSO-G20
JESD-609代码:e3/e4长度:6.5 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):12.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN/NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

74AC573MTC_NL 数据手册

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November 1988  
Revised October 1999  
74AC573 • 74ACT573  
Octal Latch with 3-STATE Outputs  
General Description  
The 74AC573 and 74ACT573 are high-speed octal latches  
with buffered common Latch Enable (LE) and buffered  
common Output Enable (OE) inputs.  
Features  
ICC and IOZ reduced by 50%  
Inputs and outputs on opposite sides of package allow-  
ing easy interface with microprocessors  
The 74AC573 and 74ACT573 are functionally identical to  
the 74AC373 and 74ACT373 but with inputs and outputs  
on opposite sides.  
Useful as input or output port for microprocessors  
Functionally identical to 74AC373 and 74ACT373  
3-STATE outputs for bus interfacing  
Outputs source/sink 24 mA  
74ACT573 has TTL-compatible inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC573SC  
74AC573SJ  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74AC573MTC  
74AC573PC  
74ACT573SC  
74ACT573SJ  
74ACT573MTC  
74ACT573PC  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20B  
M20D  
MTC20  
N20A  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
Data Inputs  
Latch Enable Input  
D0–D7  
LE  
OE  
3-STATE Output Enable Input  
3-STATE Latch Outputs  
O0–O7  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS009973  
www.fairchildsemi.com  

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