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74AC573

更新时间: 2024-11-07 22:53:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
10页 94K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

74AC573 数据手册

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74AC573  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUT NON INVERTING  
HIGH SPEED: tPD = 4.5 ns (TYP.) at VCC = 5V  
LOW POWER DISSIPATION:  
ICC = 8 µA (MAX.) at TA = 25 oC  
HIGH NOISE IMMUNITY:  
VNIH = VNIL = 28% VCC (MIN.)  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL =24 mA (MIN)  
BALANCED PROPAGATION DELAYS:  
tPLH tPHL  
OPERATING VOLTAGE RANGE:  
B
M
(Plastic Package)  
(Micro Package)  
ORDER CODES :  
74AC573B  
74AC573M  
latch enable input (LE) and an output enable  
input (OE).  
While the LE input is held at a high level, the Q  
outputs will follow the data input precisely.  
When the LE is taken low, the Q outputs will be  
latched precisely at the logic level of D input data.  
VCC (OPR) = 2V to 6V  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 573  
IMPROVED LATCH-UP IMMUNITY  
While the (OE) input is low, the 8 outputs will be  
in a normal logic state (high or low logic level)  
and while high level the outputs will be in a high  
impedance state.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The AC573 is an advanced high-speed CMOS  
OCTAL D-TYPE LATCH with 3 STATE OUTPUT  
NON INVERTING fabricated with sub-micron  
silicon gate and double-layer metal wiring C2MOS  
technology. It is ideal for low power applications  
mantaining high speed operation similar to  
equivalentBipolar Schottky TTL.  
These 8 bit D-Type latches are controlled by a  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/10  
April 1997  

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