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74AC540SJX_NL PDF预览

74AC540SJX_NL

更新时间: 2024-11-09 13:00:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
7页 98K
描述
Bus Driver, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO20,

74AC540SJX_NL 技术参数

是否Rohs认证:符合生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.84
Is Samacsys:N控制类型:ENABLE LOW
JESD-30 代码:R-PDSO-G20负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.012 A
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:3.3/5 V
Prop。Delay @ Nom-Sup:8 ns认证状态:Not Qualified
子类别:Bus Driver/Transceivers表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

74AC540SJX_NL 数据手册

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November 1988  
Revised March 2005  
74AC540  
Octal Buffer/Line Driver with 3-STATE Outputs  
General Description  
The AC540 is an octal buffer/line drivers designed to be  
employed as memory and address drivers, clock drivers  
and bus oriented transmitter/receivers.  
Features  
ICC and IOZ reduced by 50%  
3-STATE inverting outputs  
Inputs and outputs opposite side of package, allowing  
easier interface to microprocessors  
These devices are similar in function to the AC240 while  
providing flow-through architecture (inputs on opposite side  
from outputs). This pinout arrangement makes these  
devices especially useful as output ports for microproces-  
sors, allowing ease of layout and greater PC board density.  
Output source/sink 24 mA  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC540SC  
74AC540SJ  
74AC540MTC  
74AC540PC  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Truth Table  
Inputs  
OE2  
Outputs  
OE1  
I
L
H
X
L
L
X
H
L
H
X
X
L
L
Z
Z
H
H
L
HIGH Voltage Level  
LOW Voltage Level  
X
Z
Immaterial  
High Impedance  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
Ds009966  
www.fairchildsemi.com  

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