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74AC273PC PDF预览

74AC273PC

更新时间: 2024-11-18 22:35:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管PC
页数 文件大小 规格书
10页 101K
描述
Octal D-Type Flip-Flop

74AC273PC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.41
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:1330451Samacsys Pin Count:20
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Dual-In-Line Packages
Samacsys Footprint Name:20_lead PDIP N20A_1Samacsys Released Date:2018-08-27 14:19:10
Is Samacsys:N系列:AC
JESD-30 代码:R-PDIP-T20JESD-609代码:e3
长度:26.075 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:75000000 Hz
最大I(ol):0.012 A位数:8
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT APPLICABLE电源:3.3/5 V
传播延迟(tpd):14.5 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT APPLICABLE触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:125 MHz
Base Number Matches:1

74AC273PC 数据手册

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November 1988  
Revised August 2000  
74AC273 74ACT273  
Octal D-Type Flip-Flop  
General Description  
Features  
Ideal buffer for microprocessor or memory  
Eight edge-triggered D-type flip-flops  
Buffered common clock  
The AC273 and ACT273 have eight edge-triggered D-type  
flip-flops with individual D-type inputs and Q outputs. The  
common buffered Clock (CP) and Master Reset (MR) input  
load and reset (clear) all flip-flops simultaneously.  
Buffered, asynchronous master reset  
See 377 for clock enable version  
See 373 for transparent latch version  
See 374 for 3-STATE version  
The register is fully edge-triggered. The state of each D-  
type input, one setup time before the LOW-to-HIGH clock  
transition, is transferred to the corresponding flip-flop’s Q  
output.  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only  
is required and the Clock and Master Reset are common to  
all storage elements.  
Outputs source/sink 24 mA  
74ACT273 has TTL-compatible inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC273SC  
74AC273SJ  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74AC273MTC  
74AC273PC  
74ACT273SC  
74ACT273SJ  
74ACT273MTC  
74ACT273PC  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20B  
M20D  
MTC20  
N20A  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2000 Fairchild Semiconductor Corporation  
DS009954  
www.fairchildsemi.com  

74AC273PC 替代型号

型号 品牌 替代类型 描述 数据表
74AC377PC FAIRCHILD

完全替代

Octal D-Type Flip-Flop with Clock Enable
MC74AC377NG ONSEMI

功能相似

Octal D Flip−Flop with Clock Enable
CD74AC273E TI

功能相似

Octal D Flip-Flop with Reset

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暂无描述
74AC273SCXR FAIRCHILD

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Octal D-Type Flip-Flop