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74AC273LC PDF预览

74AC273LC

更新时间: 2024-11-20 05:07:59
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
8页 175K
描述
AC SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20

74AC273LC 数据手册

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August 1993  
54AC/74AC273  
Octal D Flip-Flop  
General Description  
Features  
Y
Ideal buffer for microprocessor or memory  
The ’273 has eight edge-triggered D-type flip-flops with indi-  
vidual D inputs and Q outputs. The common buffered Clock  
(CP) and Master Reset (MR) input load and reset (clear) all  
flip-flops simultaneously.  
Y
Eight edge-triggered D flip-flops  
Y
Buffered common clock  
Y
Buffered, asynchronous master reset  
Y
The register is fully edge-triggered. The state of each D in-  
put, one setup time before the LOW-to-HIGH clock tran-  
sition, is transferred to the corresponding flip-flop’s Q out-  
put.  
See ’377 for clock enable version  
Y
See ’373 for transparent latch version  
Y
See ’374 for TRI-STATE version  
Y
Outputs source/sink 24 mA  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The  
device is useful for applications where the true output only is  
required and the Clock and Master Reset are common to all  
storage elements.  
Y
’ACT has TTL-compatible inputs  
Y
Standard Military Drawing (SMD)  
Ð ’AC273: 5962-87756  
Logic Symbols  
Connection Diagrams  
Pin Assignment  
for DIP, Flatpak and SOIC  
IEEE/IEC  
TL/F/9954–1  
TL/F/9954–2  
TL/F/9954–3  
Pin Assignment  
for LCC  
Pin Names  
Description  
D D  
0
Data Inputs  
7
MR  
CP  
Master Reset  
Clock Pulse Input  
Data Outputs  
Q Q  
0
7
FACTTM is a trademark of National Semiconductor Corporation.  
TL/F/9954–4  
C
1995 National Semiconductor Corporation  
TL/F/9954  
RRD-B30M75/Printed in U. S. A.  

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