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74AC245M PDF预览

74AC245M

更新时间: 2024-11-21 22:53:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线收发器输出元件
页数 文件大小 规格书
9页 266K
描述
OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS (NON INVERTED)

74AC245M 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.28
其他特性:WITH DIRECTION CONTROL控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:AC
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.012 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 VProp。Delay @ Nom-Sup:11.5 ns
传播延迟(tpd):11.5 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:7.5 mm

74AC245M 数据手册

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74AC245  
OCTAL BUS TRANSCEIVER  
WITH 3 STATE OUTPUTS (NON INVERTED)  
HIGH SPEED: t = 4.5ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4µA(MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
50TRANSMISSION LINE DRIVING  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
DIP  
SOP  
74AC245B  
74AC245M  
V
CC  
74AC245MTR  
74AC245TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 244  
IMPROVED LATCH-UP IMMUNITY  
TSSOP  
DIR input. The enable input G can be used to  
disable the device so that the buses are effectively  
isolated..  
All floating bus terminals during HIGH-Z state  
must be held HIGH or LOW  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74AC245 is an advanced high-speed CMOS  
OCTAL  
BUS  
TRANSCEIVER  
(3-STATE)  
fabricated with sub-micron silicon gate and  
double-layer metal wiring C MOS tecnology.  
This IC is intended for two-way asynchronous  
communication between data buses and the  
direction of data transmission is determined by  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/9  

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