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74AC240PC PDF预览

74AC240PC

更新时间: 2024-11-17 22:53:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 91K
描述
Octal Buffer/Line Driver with 3-STATE Outputs

74AC240PC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.01
控制类型:ENABLE LOW系列:AC
JESD-30 代码:R-PDIP-T20JESD-609代码:e3
长度:26.075 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.012 A
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT APPLICABLE
电源:3.3/5 VProp。Delay @ Nom-Sup:9 ns
传播延迟(tpd):9 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT APPLICABLE宽度:7.62 mm
Base Number Matches:1

74AC240PC 数据手册

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November 1988  
Revised November 1999  
74AC240 74ACT240  
Octal Buffer/Line Driver with 3-STATE Outputs  
General Description  
Features  
The AC/ACT240 is an octal buffer and line driver designed  
to be employed as a memory address driver, clock driver  
and bus oriented transmitter or receiver which provides  
improved PC board density.  
ICC and IOZ reduced by 50%  
Inverting 3-STATE outputs drive bus lines or buffer  
memory address registers  
Outputs source/sink 24 mA  
ACT240 has TTL-compatible inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC240SC  
74AC240SJ  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74AC240MTC  
74AC240PC  
74ACT240SC  
74ACT240SJ  
74ACT240MTC  
74ACT240PC  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20B  
M20D  
MTC20  
N20A  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
IEEE/IEC  
Pin Names  
Description  
OE1, OE2  
I0I7  
3-STATE Output Enable Inputs  
Inputs  
O0O7  
Outputs  
Truth Tables  
Inputs  
OE1  
Outputs  
In  
(Pins 12, 14, 16, 18)  
L
L
L
H
X
H
L
H
Z
Connection Diagram  
Inputs  
OE2  
Outputs  
In  
(Pins 3, 5, 7, 9)  
L
L
L
H
X
H
L
H
Z
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = High Impedance  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS009941  
www.fairchildsemi.com  

74AC240PC 替代型号

型号 品牌 替代类型 描述 数据表
74ACQ240PC FAIRCHILD

完全替代

Quiet Series. Octal Buffer/Line Driver with 3-STATE Outputs
CD74AC240E TI

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Octal Buffer/Line Drivers, 3-State
SN74AC240N TI

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