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74AC125MTR PDF预览

74AC125MTR

更新时间: 2024-10-30 04:47:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 304K
描述
QUAD BUS BUFFERS (3-STATE)

74AC125MTR 数据手册

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January 2008  
74AC125, 74ACT125  
Quad Buffer with 3-STATE Outputs  
Features  
General Description  
I reduced by 50%  
The AC/ACT125 contains four independent non-inverting  
buffers with 3-STATE outputs.  
CC  
Outputs source/sink 24mA  
ACT125 has TTL-compatible outputs  
Ordering Information  
Order  
Number  
Package  
Number  
Package Description  
74AC125SC  
74AC125SJ  
M14A  
M14D  
MTC14  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74AC125MTC  
74AC125PC  
74ACT125SC  
74ACT125SJ  
74ACT125MTC  
74ACT125PC  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M14A  
M14D  
MTC14  
N14A  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
All packages are lead free per JEDEC: J-STD-020B standard.  
Connection Diagram  
Logic Symbol  
IEEE/IEC  
Pin Description  
Function Table  
Pin Names  
Description  
Inputs  
Output  
A , B  
Inputs  
Outputs  
n
n
A
B
O
n
n
n
O
n
L
L
L
H
Z
L
H
X
H
H = HIGH Voltage Level, L = LOW Voltage Level  
Z = HIGH Impedance, X = Immaterial  
©1988 Fairchild Semiconductor Corporation  
74AC125, 74ACT125 Rev. 1.4.1  
www.fairchildsemi.com  

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