74AC11160
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS380 – D3199, AUGUST 1988 – REVISED APRIL 1993
DW OR N PACKAGE
(TOP VIEW)
• Internal Look-Ahead for Fast Counting
• Carry Output for n-Bit Cascading
• Fully Synchronous Operation for Counting
RCO
CLR
CLK
A
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
Q
• Flow-Through Architecture to Optimize PCB
A
Q
B
Layout
GND
GND
GND
GND
B
• Center-Pin V
and GND Pin Configurations
Minimize High-Speed Switching Noise
CC
V
CC
V
CC
• EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
C
D
Q
Q
C
D
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
12 ENP
11
LOAD
ENT
description
This synchronous, presettable 4-bit decade counter features an internal carry look-ahead circuitry for
application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each other when so instructed by the count-enable
inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally
associated with asynchronous (ripple clock) counters; however, counting spikes may occur on the ripple carry
out output (RCO). A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock
input waveform.
This counter is fully programmable in that they may be preset to any number between 0 and 9. As presetting
is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree
with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function
for the 74AC11160 is synchronous and a low level at the clear input sets all four of the flip-flops outputs low,
regardless of the levels of the clock, load, or enable inputs.
If one of these decade counters is preset to a number between 10 and 15 or assumes such an invalid state when
power is applied, it will progress to the normal sequence within two counts as shown in the state diagram.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry
output. Both count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable the
ripple carry output (RCO). RCO thus enabled will produce a high-level pulse while the count is 9 (HLLH). This
high-level overflow ripple carry pulse can be used to enable successive cascaded stages. Transitions at the
ENP or ENT are allowed regardless of the level of the clock input.
This counter features a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that will
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting
the setup and hold times.
The 74AC11160 is characterized for operation from –40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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