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74AC11002

更新时间: 2024-01-03 05:05:59
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
5页 70K
描述
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

74AC11002 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:0.300 INCH, PLASTIC, DIP-16针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.81Is Samacsys:N
其他特性:CENTER PIN VCC AND GND系列:AC
JESD-30 代码:R-PDIP-T16长度:19.305 mm
负载电容(CL):50 pF逻辑集成电路类型:NOR GATE
最大I(ol):0.024 A功能数量:4
输入次数:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 VProp。Delay @ Nom-Sup:9.9 ns
传播延迟(tpd):6.4 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

74AC11002 数据手册

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54AC11002, 74AC11002  
QUADRUPLE 2-INPUT POSITIVE-NOR GATES  
SCAS024A – JUNE 1987 – REVISED APRIL 1993  
54AC11002 . . . J PACKAGE  
74AC11002 . . . D OR N PACKAGE  
(TOP VIEW)  
Flow-Through Architecture Optimizes  
PCB Layout  
Center-Pin V  
and GND Configuration  
Minimizes High-Speed Switching Noise  
CC  
1B  
2A  
2B  
V
1A  
1Y  
2Y  
GND  
GND  
3Y  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
500-mA Typical Latch-Up Immunity  
at 125°C  
CC  
V
CC  
3A  
3B  
4A  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
4Y  
4B  
54AC11002 . . . FK PACKAGE  
(TOP VIEW)  
description  
These devices contain four independent 2-input  
NOR gates. They perform the Boolean functions  
Y = A B or Y = A + B in positive logic.  
3
2
1
20 19  
18  
3B  
4A  
NC  
4B  
4Y  
2A  
1B  
NC  
1A  
1Y  
The 54AC11002 is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The 74AC11002 is characterized for  
operation from 40°C to 85°C.  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
X
H
L
NC – No internal connection  
H
X
L
L
L
H
logic symbol  
logic diagram (positive logic)  
1
1
1A  
16  
1A  
2
2
3
6
7
1  
1Y  
16  
1Y  
2Y  
3Y  
4Y  
1B  
1B  
15  
2A  
14  
15  
2A  
3
6
2Y  
3Y  
2B  
11  
14  
2B  
3A  
10  
11  
3A  
3B  
9
10  
3B  
4A  
8
9
4B  
4A  
7
4Y  
8
4B  
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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