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74AC00 PDF预览

74AC00

更新时间: 2024-02-26 11:43:55
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德州仪器 - TI 输入元件
页数 文件大小 规格书
5页 81K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

74AC00 技术参数

生命周期:Contact Manufacturer包装说明:TSSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.63系列:AC
JESD-30 代码:R-PDSO-G14长度:5 mm
逻辑集成电路类型:NAND GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):11 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

74AC00 数据手册

 浏览型号74AC00的Datasheet PDF文件第2页浏览型号74AC00的Datasheet PDF文件第3页浏览型号74AC00的Datasheet PDF文件第4页浏览型号74AC00的Datasheet PDF文件第5页 
SN54AC00, SN74AC00  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
SCAS524C – AUGUST 1995 – REVISED SEPTEMBER 1996  
SN54AC00 . . . J OR W PACKAGE  
SN74AC00 . . . D, DB, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), DIP  
(N) Packages, Ceramic Chip Carriers (FK),  
Flat (W), and DIP (J) Packages  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
2Y  
GND  
8
The ‘AC00 contain four independent 2-input NAND  
gates. Each gate performs the Boolean function of  
Y = A B or Y = A + B in positive logic.  
SN54AC00 . . . FK PACKAGE  
(TOP VIEW)  
The SN54AC00 is characterized for operation over  
the full military temperature range of 55°C to 125°C.  
The SN74AC00 is characterized for operation from  
40°C to 85°C.  
3
2
1
20 19  
18  
1Y  
NC  
2A  
4A  
NC  
4Y  
4
5
6
7
8
FUNCTION TABLE  
(each gate)  
17  
16  
INPUTS  
NC  
2B  
15 NC  
14  
9 10 11 12 13  
OUTPUT  
Y
A
H
L
B
H
X
L
3B  
L
H
H
X
NC – No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1A  
2
&
A
B
3
6
Y
1Y  
2Y  
3Y  
4Y  
1B  
4
2A  
5
2B  
9
3A  
10  
3B  
12  
4A  
13  
4B  
8
11  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, DB, J, N, PW, and W packages.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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