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74ABT899CSC PDF预览

74ABT899CSC

更新时间: 2024-11-06 22:56:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
16页 130K
描述
9-Bit Latchable Transceiver with Parity Generator/Checker

74ABT899CSC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP28,.4
针数:28Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.23
Is Samacsys:N其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:ABTJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:17.9 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.064 A湿度敏感等级:3
位数:9功能数量:1
端口数量:2端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP28,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):34 mA
Prop。Delay @ Nom-Sup:4.8 ns传播延迟(tpd):4.6 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:7.5 mm
Base Number Matches:1

74ABT899CSC 数据手册

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November 1992  
Revised January 1999  
74ABT899  
9-Bit Latchable Transceiver  
with Parity Generator/Checker  
Ability to simultaneously generate and check parity  
General Description  
May be used in systems applications in place of the  
543 and 280  
The ABT899 is a 9-bit to 9-bit parity transceiver with trans-  
parent latches. The device can operate as a feed-through  
transceiver or it can generate/check parity from the 8-bit  
data busses in either direction.  
May be used in system applications in place of the  
657 and 373 (no need to change T/R to check parity)  
Guaranteed output skew  
The ABT899 features independent latch enables for the A-  
to-B direction and the B-to-A direction, a select pin for  
ODD/EVEN parity, and separate error signal output pins for  
checking parity.  
Guaranteed multiple output switching specifications  
Output switching specified for both 50 pF and  
250 pF loads  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Features  
Latchable transceiver with output sink of 64 mA  
Guaranteed latchup protection  
Option to select generate parity and check or  
High impedance glitch free bus loading during entire  
“feed-through” data/parity in directions A-to-B or B-to-A  
power up and power down cycle  
Independent latch enables for A-to-B and B-to-A  
Nondestructive hot insertion capability  
directions  
Disable time less than enable time to avoid bus  
Select pin for ODD/EVEN parity  
contention  
ERRA and ERRB output pins for parity checking  
Ordering Code:  
Order Number Package Number  
Package Description  
74ABT899CSC  
74ABT899CMSA  
74ABT899CQC  
M28B  
MSA28  
V28A  
28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body  
28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pin Assignment for  
SOIC and SSOP  
Connection Diagrams  
Pin Assignment  
for PLCC  
© 1999 Fairchild Semiconductor Corporation  
DS011509.prf  
www.fairchildsemi.com  

74ABT899CSC 替代型号

型号 品牌 替代类型 描述 数据表
74ABT899CSCX FAIRCHILD

完全替代

Single 8-bit Bus Transceiver
74ABT899CMSAX FAIRCHILD

完全替代

Single 8-bit Bus Transceiver
74ABT899CMSA FAIRCHILD

完全替代

9-Bit Latchable Transceiver with Parity Generator/Checker

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