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74ABT841DB,118 PDF预览

74ABT841DB,118

更新时间: 2024-01-28 01:23:45
品牌 Logo 应用领域
恩智浦 - NXP 驱动信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
6页 48K
描述
74ABT841 - 10-bit bus interface latch; 3-state SSOP2 24-Pin

74ABT841DB,118 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP2包装说明:SSOP, SSOP24,.3
针数:24Reach Compliance Code:unknown
风险等级:5.56其他特性:POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTION; WITH POWER-UP RESET
系列:ABTJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:8.2 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.064 A湿度敏感等级:1
位数:10功能数量:1
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP24,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):38 mAProp。Delay @ Nom-Sup:6.2 ns
传播延迟(tpd):6.7 ns认证状态:Not Qualified
座面最大高度:2 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:5.3 mm
Base Number Matches:1

74ABT841DB,118 数据手册

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Philips Semiconductors  
Product specification  
10-bit bus interface latch (3-State)  
74ABT841  
FEATURES  
High speed parallel latches  
DESCRIPTION  
The 74ABT841 Bus interface register is designed to provide extra  
data width for wider data/address paths of buses carrying parity.  
Extra data width for wide address/data paths or buses carrying  
The 74ABT841 consists of ten D-type latches with 3-State outputs.  
The flip-flops appear transparent to the data when Latch Enable  
(LE) is High. This allows asynchronous operation, as the output  
transition follows the data in transition. On the LE High-to-Low  
transition, the data that meets the setup and hold time is latched.  
parity  
Ideal where high speed, light loading, or increased fan-in are  
required with MOS microprocessors  
Slim DIP 300 mil package  
Data appears on the bus when the Output Enable (OE) is Low.  
When OE is High the output is in the High-impedance state.  
Broadside pinout  
Output capability: +64mA/–32mA  
Latch-up protection exceeds 500mA per Jedec Std 17  
ESD protection exceeds 2000 V per MIL STD 883 Method 3015  
and 200 V per Machine Model  
Power-up 3-State  
Power-up reset  
QUICK REFERENCE DATA  
CONDITIONS  
= 25°C; GND = 0V  
SYMBOL  
PARAMETER  
TYPICAL  
UNIT  
T
amb  
t
t
Propagation delay  
Dn to Qn  
PLH  
PHL  
C = 50pF; V = 5V  
4.1  
4
ns  
pF  
pF  
nA  
L
CC  
C
Input capacitance  
V = 0V or V  
I CC  
IN  
Outputs disabled;  
= 0V or V  
C
Output capacitance  
Total supply current  
7
OUT  
CCZ  
V
O
CC  
I
Outputs disabled; V = 5.5V  
500  
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE OUTSIDE NORTH AMERICA  
NORTH AMERICA  
74ABT841 N  
DWG NUMBER  
SOT222-1  
24-Pin Plastic DIP  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
74ABT841 N  
74ABT841 D  
74ABT841 DB  
74ABT841 PW  
24-Pin plastic SO  
74ABT841 D  
SOT137-1  
24-Pin Plastic SSOP Type II  
24-Pin Plastic TSSOP Type I  
74ABT841 DB  
74ABT841PW DH  
SOT340-1  
SOT355-1  
PIN CONFIGURATION  
PIN DESCRIPTION  
PIN NUMBER  
SYMBOL  
FUNCTION  
24  
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
1
2
3
4
5
6
7
8
9
V
CC  
Output enable input  
(active-Low)  
1
OE  
23 Q0  
22 Q1  
21 Q2  
20 Q3  
19 Q4  
18 Q5  
17 Q6  
16 Q7  
2, 3, 4, 5, 6,  
7, 8, 9, 10, 11  
D0-D9  
Q0-Q9  
Data inputs  
23, 22, 21, 20, 19,  
18, 17, 16, 15, 14  
Data outputs  
TOP VIEW  
Latch enable input (active  
falling edge)  
13  
LE  
12  
24  
GND  
Ground (0V)  
V
CC  
Positive supply voltage  
D8 10  
D9 11  
15  
14  
13  
Q8  
Q9  
LE  
GND 12  
SA00247  
1
1995 Sep 06  
853-1628 15703  

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