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74ABT657D,602 PDF预览

74ABT657D,602

更新时间： 2024-11-18 14:48:35
品牌 Logo 应用领域
恩智浦 - NXP 信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
17页 108K
描述
74ABT657 - Octal transceiver with parity generator/checker; 3-state SOP 24-Pin

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74ABT657D,602 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：SOP包装说明：7.50 MM, PLASTIC, MS-013, SOT137-1, SOP-24
针数：24Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.5
Is Samacsys：N其他特性：WITH DIRECTION CONTROL; PARITY GENERATION/ERROR DETECTION
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：ABTJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：15.4 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.064 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：30 mA
Prop。Delay @ Nom-Sup：5.5 ns传播延迟（tpd）：4.6 ns
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
翻译：N/A宽度：7.5 mm
Base Number Matches：1

74ABT657D,602 数据手册

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74ABT657  
Octal transceiver with parity generator/checker; 3-state  
Rev. 03 — 15 March 2010  
Product data sheet  
1. General description  
The 74ABT657 high-performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-state outputs  
and an 8-bit parity generator/checker, and is intended for bus-oriented applications. The  
buffers have a guaranteed current sinking capability of 64 mA. The Transmit/Receive input  
(pin T/R) determines the direction of the data flow through the bidirectional transceivers.  
Transmit (active HIGH) enables data from A ports to B ports; Receive (active LOW)  
enables data from B ports to A ports.  
When Output Enable input (pin OE) is HIGH, both A and B ports are high-impedance. The  
parity select input (pin ODD/EVEN) allows the user to generate either an odd or even  
parity output, depending on the system. Pin PARITY is an output from the  
generator/checker when transmitting from port A to port B (pin T/R = HIGH) and an input  
when receiving from port B to port A port (pin T/R = LOW).  
In transmit mode (pin T/R = HIGH) port A is polled to determine the number of HIGH  
inputs on port A. Pin PARITY output goes to the logic state determined by the setting of  
pin ODD/EVEN and by the number of HIGH inputs on port A. For example, if pin  
ODD/EVEN is set LOW (even parity) and the number of HIGH inputs on port A is odd, pin  
PARITY output goes HIGH, transmitting even parity. If the number of HIGH inputs on port  
A is even, pin PARITY output goes LOW, keeping even parity.  
In receive mode (pin T/R = LOW) port B is polled to determine the number of HIGH inputs  
on port B. If pin ODD/EVEN is LOW (even parity) and the number of HIGH inputs on port  
B is:  
• Odd and pin PARITY input is HIGH, pin ERROR is HIGH, indicating no error  
• Even and pin PARITY input is HIGH, pin ERROR goes LOW, indicating an error  
2. Features and benefits  
I Combinational functions in one package  
I Low static and dynamic power dissipation with high speed and high output drive  
I Output capability: +64 mA and −32 mA  
I Power-up 3-state  
I Latch-up protection exceeds 500 mA per JESD78B class II level A  
I ESD protection:  
N HBM JESD22-A114F exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
 
 
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