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74ABT652CMTC PDF预览

74ABT652CMTC

更新时间: 2024-11-17 22:56:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
10页 94K
描述
Octal Transceivers and Registers with 3-STATE Outputs

74ABT652CMTC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP24,.25
针数:24Reach Compliance Code:unknown
风险等级:5.6其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:ABTJESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:7.8 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.064 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):30 mA
Prop。Delay @ Nom-Sup:4.5 ns传播延迟(tpd):4.9 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:4.4 mm

74ABT652CMTC 数据手册

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November 1992  
Revised January 1999  
74ABT652  
Octal Transceivers and Registers with 3-STATE Outputs  
A and B output sink capability of 64 mA, source  
capability of 32 mA  
General Description  
The ABT652 consists of bus transceiver circuits with D-  
Guaranteed output skew  
type flip-flops and control circuitry arranged for multiplexed  
transmission of data directly from the input bus or from the  
Guaranteed multiple output switching specifications  
internal registers. Data on the A or B bus will be clocked  
into the registers as the appropriate clock pin goes to HIGH  
logic level. Output Enable pins (OEAB, OEBA) are pro-  
vided to control the transceiver function.  
Output switching specified for both 50 pF and  
250 pF loads  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Guaranteed latchup protection  
Features  
High impedance glitch free bus loading during entire  
Independent registers for A and B buses  
power up and power down cycle  
Multiplexed real-time and stored data  
Nondestructive hot insertion capability  
Ordering Code:  
Order Number Package Number  
Package Description  
74ABT652CSC  
74ABT652CMSA  
74ABT652CMTC  
M24B  
MSA24  
MTC24  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body  
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Assignment for  
SOIC, SSOP and TSSOP  
Pin Names  
A0–A7  
Description  
Data Register A Inputs/3-STATE Outputs  
Data Register B Inputs/3-STATE Outputs  
B0–B7  
CPAB, CPBA Clock Pulse Inputs  
SAB, SBA Select Inputs  
OEAB, OEBA Output Enable Inputs  
© 1999 Fairchild Semiconductor Corporation  
DS011512.prf  
www.fairchildsemi.com  

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