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74ABT646APW,112 PDF预览

74ABT646APW,112

更新时间: 2024-11-06 14:50:15
品牌 Logo 应用领域
恩智浦 - NXP 信息通信管理光电二极管逻辑集成电路触发器
页数 文件大小 规格书
19页 108K
描述
74ABT646A - Octal bus transceiver/register; 3-state TSSOP2 24-Pin

74ABT646APW,112 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP2包装说明:TSSOP, TSSOP24,.25
针数:24Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.5
其他特性:WITH DIRECTION CONTROL控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:ABT
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:7.8 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.064 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:5.4 ns传播延迟(tpd):5.6 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
翻译:N/A触发器类型:POSITIVE EDGE
宽度:4.4 mmBase Number Matches:1

74ABT646APW,112 数据手册

 浏览型号74ABT646APW,112的Datasheet PDF文件第2页浏览型号74ABT646APW,112的Datasheet PDF文件第3页浏览型号74ABT646APW,112的Datasheet PDF文件第4页浏览型号74ABT646APW,112的Datasheet PDF文件第5页浏览型号74ABT646APW,112的Datasheet PDF文件第6页浏览型号74ABT646APW,112的Datasheet PDF文件第7页 
74ABT646A  
Octal bus transceiver/register; 3-state  
Rev. 03 — 15 March 2010  
Product data sheet  
1. General description  
The 74ABT646A high-performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT646A transceiver/register consists of bus transceiver circuits with 3-state  
outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of  
data directly from the input bus or the internal registers. Data on the A bus or B bus will be  
clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH.  
Output Enable (OE) and Direction (DIR) pins are provided to control the transceiver  
function. In the transceiver mode, data present at the high-impedance port may be stored  
in either the A or B register or both.  
The Select (SAB, SBA) pins determine whether data is stored or transferred through the  
device in real-time. The DIR pin determines which bus receives data when OE is active  
(LOW). In isolation mode (OE = HIGH), data from bus A may be stored in the B register  
and/or data from bus B may be stored in the A register. When an output function is  
disabled, the input function is still enabled and may be used to store and transmit data.  
Only one of the two buses, A or B, may be driven at a time. The examples in Figure 5  
“Real time bus transfer and storage” on page 6 demonstrate the four fundamental bus  
management functions that can be performed with the 74ABT646A.  
2. Features and benefits  
I Combines 74ABT245 and 74ABT373A type functions in one device  
I Independent registers for A and B buses  
I Multiplexed real-time and stored data  
I Live insertion and extraction permitted  
I Output capability: +64 mA to 32 mA  
I Power-up 3-state  
I Power-up reset  
I Latch-up protection exceeds 500 mA per JESD78B class II level A  
I ESD protection:  
N HBM JESD22-A114F exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
 
 

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