74ABT544PW

更新时间： 2024-02-02 08:16:09

品牌	Logo	应用领域
恩智浦 - NXP		逻辑集成电路光电二极管
页数	文件大小	规格书
19页	116K
描述
Octal latched transceiver with dual enable; inverting; 3-state

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74ABT544PW 数据手册

74ABT544

Octal latched transceiver with dual enable; inverting; 3-state

Rev. 03 — 20 April 2005

Product data sheet

1. General description

The 74ABT544 high-performance BiCMOS device combines low static and dynamic

power dissipation with high speed and high output drive.

The 74ABT544 octal latched transceiver contains two sets of D-type latches for temporary

storage of data ﬂowing in either direction. Separate latch enable (LEAB and LEBA) and

output enable (OEAB and OEBA) inputs are provided for each register to permit

independent control of data transfer in either direction. The outputs are guaranteed to sink

64 mA.

The 74ABT544 contains two sets of eight D-type latches, with separate control pins for

each set. Using data ﬂow from A to B as an example, when the A-to-B enable (EAB) input

and the A-to-B latch enable (LEAB) input are LOW, the A-to-B path is transparent.

A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches

where it is stored and the B outputs no longer change with the A inputs. With EAB and

OEAB both LOW, the 3-state B output buffers are active and invert the data present at the

outputs of the A latches.

Control of data ﬂow from B to A is similar, but using the EBA, LEBA and OEBA inputs.

2. Features

■ Combines 74ABT640 and 74ABT373 type functions in one device

■ 8-bit octal transceiver with D-type latch

■ Back-to-back registers for storage

■ Separate controls for data ﬂow in each direction

■ Output capability: +64 mA and −32 mA

■ Live insertion and extraction permitted

■ Power-up 3-state

■ Power-up reset

■ Latch-up protection:

◆ JESD78: exceeds 500 mA

■ ESD protection:

◆ MIL STD 883 method 3015: exceeds 2000 V

◆ Machine model: exceeds 200 V

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