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74ABT541 PDF预览

74ABT541

更新时间: 2024-01-27 16:04:37
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
10页 126K
描述
Octal Buffer/Line Driver with 3-STATE Outputs

74ABT541 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Obsolete包装说明:TSSOP,
Reach Compliance Code:compliant风险等级:5.14
其他特性:WITH DUAL OUTPUT ENABLE系列:ABT
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260最大电源电流(ICC):30 mA
传播延迟(tpd):4.6 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

74ABT541 数据手册

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September 1992  
Revised March 2005  
74ABT541  
Octal Buffer/Line Driver with 3-STATE Outputs  
General Description  
The ABT541 is an octal buffer and line driver with 3-STATE  
Features  
Non-inverting buffers  
outputs designed to be employed as  
a memory and  
Output sink capability of 64 mA, source capability of  
32 mA  
address driver, clock driver, or bus-oriented transmitter/  
receiver. The ABT541 is similar to the ABT244 with broad-  
side pinout.  
Guaranteed output skew  
Guaranteed multiple output switching specifications  
Output switching specified for both 50 pF and 250 pF  
loads  
Guaranteed simultaneous switching, noise level and  
dynamic threshold performance  
Guaranteed latchup protection  
High impedance, glitch free bus loading during entire  
power up and power down cycle  
Nondestructive hot insertion capability  
Flow-through pinout for ease of PC board layout  
Disable time less than enable time to avoid bus  
contention  
Ordering Code:  
Order Number Package Number  
Package Description  
74ABT541CSC  
74ABT541CSJ  
74ABT541CMSA  
74ABT541CMTC  
74ABT541CPC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
MSA20  
MTC20  
N20A  
Devices also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Connection Diagram  
Pin Descriptions  
Pin Names  
OE1, OE2  
Description  
Output Enable Input (Active LOW)  
I0I7  
Inputs  
O0O7  
Outputs  
Truth Table  
Inputs  
Outputs  
OE1  
OE2  
I
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
L
H
L
HIGH Voltage Level  
LOW Voltage Level  
X
Z
Immaterial  
High Impedance  
© 2005 Fairchild Semiconductor Corporation  
DS011501  
www.fairchildsemi.com  

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