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74ABT16952DGGRE4

更新时间： 2024-11-10 21:54:15
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德州仪器 - TI 逻辑集成电路光电二极管输出元件信息通信管理
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10页 169K
描述
16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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74ABT16952DGGRE4 数据手册

 浏览型号74ABT16952DGGRE4的Datasheet PDF文件第2页浏览型号74ABT16952DGGRE4的Datasheet PDF文件第3页浏览型号74ABT16952DGGRE4的Datasheet PDF文件第4页浏览型号74ABT16952DGGRE4的Datasheet PDF文件第5页浏览型号74ABT16952DGGRE4的Datasheet PDF文件第6页浏览型号74ABT16952DGGRE4的Datasheet PDF文件第7页 
SN54ABT16952, SN74ABT16952  
16-BIT REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS082C – FEBRUARY 1991 – REVISED JANUARY 1997  
SN54ABT16952 . . . WD PACKAGE  
SN74ABT16952 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1OEAB  
1CLKAB  
1CLKENAB  
GND  
1OEBA  
1
2
3
4
5
6
7
8
9
56  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
55 1CLKBA  
54 1CLKENBA  
53 GND  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
1A1  
1A2  
52 1B1  
at V  
= 5 V, T = 25°C  
CC  
A
51 1B2  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
V
50  
V
CC  
CC  
1A3  
1A4  
1A5 10  
GND 11  
1A6 12  
49 1B3  
48 1B4  
47 1B5  
46 GND  
45 1B6  
Flow-Through Architecture Optimizes PCB  
Layout  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
description  
The ’ABT16952 are 16-bit registered transceivers  
that contain two sets of D-type flip-flops for  
temporary storage of data flowing in either  
direction. The’ABT16952canbeusedastwo8-bit  
transceivers or one 16-bit transceiver. Data on the  
A or B bus is stored in the registers on the  
low-to-high transition of the clock (CLKAB or  
CLKBA) input provided that the clock-enable  
(CLKENAB or CLKENBA) input is low. Taking the  
output-enable (OEAB or OEBA) input low  
accesses the data on either port.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2CLKENBA  
2CLKBA  
2OEBA  
2CLKENAB  
2CLKAB  
2OEAB  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54ABT16952 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ABT16952 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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74ABT16952DGGRE4 替代型号

型号 品牌 替代类型 描述 数据表
74ABT16952DGGRG4 TI

完全替代

 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
CY74FCT16952CTPACT TI

类似代替

 16-Bit Registered Transceivers
SN74ABT16952DGGR TI

类似代替

 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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