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74ABT16952CMTD PDF预览

74ABT16952CMTD

更新时间: 2024-11-10 22:45:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
7页 75K
描述
16-Bit Registered Transceiver with 3-STATE Outputs

74ABT16952CMTD 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP56,.3,20
针数:56Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.38
Is Samacsys:N其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:ABTJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:14 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.064 A湿度敏感等级:2
位数:8功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):60 mA
Prop。Delay @ Nom-Sup:5.3 ns传播延迟(tpd):5.3 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:6.1 mmBase Number Matches:1

74ABT16952CMTD 数据手册

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November 1993  
Revised January 1999  
74ABT16952  
16-Bit Registered Transceiver with 3-STATE Outputs  
General Description  
Features  
The ABT16952 is a 16-bit registered transceiver. Two 8-bit  
back to back registers store data flowing in both directions  
between two bidirectional buses. Separate clock, clock  
enable and 3-STATE output enable signals are provided for  
each register. The output pins are guaranteed to source 32  
mA and to sink 64 mA.  
Separate clock, clock enable and 3-STATE output  
enable provided for each register  
A and B output sink capability of 64 mA source capability  
of 32 mA  
Guaranteed latchup protection  
High impedance glitch free bus loading during entire  
power up and power down cycle  
Nondestructive hot insertion capability  
Ordering Code:  
Order Number  
74ABT16952CSSC  
74ABT16952CMTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.  
Pin Descriptions  
Connection Diagram  
Pin Assignment for SSOP  
Pin Names  
Description  
A0–A15  
Data Register A Inputs/  
B-Register 3-STATE Outputs  
Data Register B Inputs/  
A-Register 3-STATE Outputs  
Clock Pulse Inputs  
B0–B15  
CPABn, CPBAn  
CEAn, CEBn  
Clock Enable  
Output Enable Inputs  
OEABn, OEBAn  
Output Control  
OE  
Internal  
Q
Output  
Function  
H
L
L
X
L
Z
L
Disable Outputs  
Enable Outputs  
H
H
Register Function Table  
(Applies to A or B Register)  
Inputs  
Internal  
D
X
L
CP  
CE  
H
Q
NC  
L
Function  
Hold Data  
Load Data  
X
L
H
L
H
H = HIGH Voltage Level  
L = LOW Voltage Level  
Z = HIGH Impedance  
= LOW-to-HIGH Transition  
X = Immaterial  
NC = No Change  
© 1999 Fairchild Semiconductor Corporation  
DS011647.prf  
www.fairchildsemi.com  

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