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74ABT16543CSSC PDF预览

74ABT16543CSSC

更新时间: 2024-11-27 22:45:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
7页 74K
描述
16-Bit Registered Transceiver with 3-STATE Outputs

74ABT16543CSSC 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP56,.4
针数:56Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.32
Is Samacsys:N其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:ABTJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:18.415 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.064 A湿度敏感等级:1
位数:8功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):60 mA
Prop。Delay @ Nom-Sup:5.7 ns传播延迟(tpd):5.5 ns
认证状态:Not Qualified座面最大高度:2.74 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:7.5 mm
Base Number Matches:1

74ABT16543CSSC 数据手册

 浏览型号74ABT16543CSSC的Datasheet PDF文件第2页浏览型号74ABT16543CSSC的Datasheet PDF文件第3页浏览型号74ABT16543CSSC的Datasheet PDF文件第4页浏览型号74ABT16543CSSC的Datasheet PDF文件第5页浏览型号74ABT16543CSSC的Datasheet PDF文件第6页浏览型号74ABT16543CSSC的Datasheet PDF文件第7页 
October 1993  
Revised January 1999  
74ABT16543  
16-Bit Registered Transceiver with 3-STATE Outputs  
General Description  
Features  
The ABT16543 16-bit transceiver contains two sets of D-  
type latches for temporary storage of data flowing in either  
direction. Separate Latch Enable and Output Enable inputs  
are provided for each register to permit independent con-  
trol of inputting and outputting in either direction of data  
flow. Each byte has separate control inputs, which can be  
shorted together for full 16-bit operation.  
Back-to-back registers for storage  
Bidirectional data path  
A and B outputs have current sourcing capability of 32  
mA and current sinking capability of 64 mA  
Separate control logic for each byte  
16-bit version of the ABT543  
Separate controls for data flow in each direction  
Guaranteed latchup protection  
High impedance glitch free bus loading during entire  
power up and power down cycle  
Nondestructive hot insertion capability  
Ordering Code:  
Order Number  
74ABT16543CSSC  
74ABT16543CMTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Assignment for SSOP and TSSOP  
Pin Names  
OEABn  
OEBAn  
CEABn  
CEBAn  
LEABn  
Description  
A-to-B Output Enable Input (Active LOW)  
B-to-A Output Enable Input (Active LOW)  
A-to-B Enable Input (Active LOW)  
B-to-A Enable Input (Active LOW)  
A-to-B Latch Enable Input (Active LOW)  
B-to-A Latch Enable Input (Active LOW)  
A-to-B Data Inputs or  
LEBAn  
A0–A15  
B-to-A 3-STATE Outputs  
B0–B15  
B-to-A Data Inputs or  
A-to-B 3-STATE Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS011646.prf  
www.fairchildsemi.com  

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