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74ABT16501CSSCX PDF预览

74ABT16501CSSCX

更新时间： 2024-11-25 23:23:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
7页 70K
描述
18-Bit Bus Transceiver

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中文翻译

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74ABT16501CSSCX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP, SSOP56,.4
针数：56Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.47
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ABT
JESD-30 代码：R-PDSO-G56JESD-609代码：e3
长度：18.415 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：68 mA
Prop。Delay @ Nom-Sup：4.6 ns传播延迟（tpd）：5.3 ns
认证状态：Not Qualified座面最大高度：2.74 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：7.5 mm

74ABT16501CSSCX 数据手册

 浏览型号74ABT16501CSSCX的Datasheet PDF文件第2页浏览型号74ABT16501CSSCX的Datasheet PDF文件第3页浏览型号74ABT16501CSSCX的Datasheet PDF文件第4页浏览型号74ABT16501CSSCX的Datasheet PDF文件第5页浏览型号74ABT16501CSSCX的Datasheet PDF文件第6页浏览型号74ABT16501CSSCX的Datasheet PDF文件第7页 
January 1995  
Revised January 1999  
74ABT16501  
18-Bit Universal Bus Transceivers with 3-STATE Outputs  
plementary (OEAB is active HIGH and OEBA is active  
LOW).  
General Description  
The ABT16501 18-bit universal bus transceiver combines  
To ensure the high-impedance state during power up or  
D-type latches and D-type flip-flops to allow data flow in  
power down, OE inputs should be tied to GND through a  
transparent, latched, and clocked modes.  
pulldown resistor; the minimum value of the resistor is  
Data flow in each direction is controlled by output-enable  
determined by the current-sourcing capability of the driver.  
(OEAB and OEBA), latch-enable (LEAB and LEBA), and  
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the  
device operates in the transparent mode when LEAB is  
Features  
■ Combines D-Type latches and D-Type flip-flops for oper-  
ation in transparent, latched, or clocked mode  
HIGH. When LEAB is LOW, the A data is latched if CLKAB  
is held at a HIGH or LOW logic level. If LEAB is LOW, the A  
bus data is stored in the latch/flip-flop on the LOW-to-HIGH  
transition of CLKAB. Output-enable OEAB is active-high.  
When OEAB is HIGH, the outputs are active. When OEAB  
is LOW, the outputs are in the high-impedance state.  
■ Flow-through architecture optimizes PCB layout  
■ Guaranteed latch-up protection  
■ High impedance glitch free bus loading during entire  
power up and power down cycle  
Data flow for B to A is similar to that of A to B but uses  
OEBA, LEBA, and CLKBA. The output enables are com-  
■ Non-destructive hot insertion capability  
Ordering Code:  
Order Number  
74ABT16501CSSC  
74ABT16501CMTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Devices also available in Tape or Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table (Note 1)  
Inputs  
Output  
Pin Assignment for SSOP  
OEAB  
LEAB CLKAB  
A
X
L
B
L
X
H
H
L
X
X
X
↑
Z
H
H
H
H
H
H
L
H
L
H
L
L
↑
H
X
X
H
L
H
L
B0 (Note 2)  
B0 (Note 3)  
L
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,  
LEBA, and CLKBA.  
Note 2: Output level before the indicated steady-state input conditions  
were established.  
Note 3: Output level before the indicated steady-state input conditions  
were established, provided that CLKAB was HIGH before LEAB went LOW.  
© 1999 Fairchild Semiconductor Corporation  
DS011690.prf  
www.fairchildsemi.com  
1234567

中文翻译

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74ABT16501CSSCX 替代型号

型号 品牌 替代类型 描述 数据表
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