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74ABT16500CSSCX PDF预览

74ABT16500CSSCX

更新时间： 2024-02-20 19:31:32
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
9页 76K
描述
18-Bit Bus Transceiver

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74ABT16500CSSCX 技术参数

生命周期：Transferred包装说明：SSOP,
Reach Compliance Code：unknown风险等级：5.66
Is Samacsys：N其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列：ABTJESD-30 代码：R-PDSO-G56
长度：18.415 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH最大电源电流（ICC）：68 mA
传播延迟（tpd）：8.5 ns认证状态：Not Qualified
座面最大高度：2.74 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

74ABT16500CSSCX 数据手册

 浏览型号74ABT16500CSSCX的Datasheet PDF文件第2页浏览型号74ABT16500CSSCX的Datasheet PDF文件第3页浏览型号74ABT16500CSSCX的Datasheet PDF文件第4页浏览型号74ABT16500CSSCX的Datasheet PDF文件第5页浏览型号74ABT16500CSSCX的Datasheet PDF文件第6页浏览型号74ABT16500CSSCX的Datasheet PDF文件第7页 
April 1993  
Revised January 1999  
74ABT16500  
18-Bit Universal Bus Transceivers with 3-STATE Outputs  
plementary (OEAB is active HIGH and OEBA is active  
LOW).  
General Description  
To ensure the high-impedance state during power up or  
power down, OE should be tied to GND through a pulldown  
resistor; the minimum value of the resistor is determined by  
the current-sourcing capability of the driver.  
The ABT16500 18-bit universal bus transceiver combines  
D-type latches and D-type flip-flops to allow data flow in  
transparent, latched, and clocked modes.  
Data flow in each direction is controlled by output-enable  
(OEAB and OEBA), latch-enable (LEAB and LEBA), and  
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the  
device operates in the transparent mode when LEAB is  
HIGH. When LEAB is LOW, the A data is latched if CLKAB  
is held at a HIGH or LOW logic level. If LEAB is LOW, the A  
bus data is stored in the latch/flip-flop on the HIGH-to-LOW  
transition of CLKAB. Output-enable OEAB is active-high.  
When OEAB is HIGH, the outputs are active. When OEAB  
is LOW, the outputs are in the high-impedance state.  
Features  
■ Combines D-Type latches and D-Type flip-flops for  
operation in transparent, latched, or clocked mode  
■ Flow-through architecture optimizes PCB layout  
■ Guaranteed latch-up protection  
■ High impedance glitch free bus loading during entire  
power up and power down cycle  
■ Non-destructive hot insertion capability  
Data flow for B to A is similar to that of A to B but uses  
OEBA, LEBA, and CLKBA. The output enables are com-  
Ordering Code:  
Order Number  
74ABT16500CSSC  
74ABT16500CMTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.  
Connection Diagram  
Function Table (Note 1)  
Inputs  
Output  
Pin Assignment for SSOP  
OEAB  
LEAB CLKAB  
A
X
L
B
L
X
H
H
L
X
X
X
↓
Z
H
H
H
H
H
H
L
H
L
H
L
L
↓
H
X
X
H
L
H
L
B0 (Note 2)  
B0 (Note 3)  
L
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,  
LEBA, and CLKBA.  
Note 2: Output level before the indicated steady-state input conditions  
were established.  
Note 3: Output level before the indicated steady-state input conditions  
were established, provided that CLKAB was LOW before LEAB went LOW.  
© 1999 Fairchild Semiconductor Corporation  
DS011581.prf  
www.fairchildsemi.com  
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