5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> 74ABT16500CMTD
74ABT16500CMTD PDF预览

74ABT16500CMTD

更新时间： 2024-11-25 22:45:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
9页 76K
描述
18-Bit Universal Bus Transceivers with 3-STATE Outputs

阅读下载

中文翻译

获取价格

74ABT16500CMTD 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP56,.3,20
针数：56Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.37
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ABT
JESD-30 代码：R-PDSO-G56JESD-609代码：e3
长度：14 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.064 A
湿度敏感等级：2位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：68 mAProp。Delay @ Nom-Sup：4.6 ns
传播延迟（tpd）：5.3 ns认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：NEGATIVE EDGE宽度：6.1 mm
Base Number Matches：1

74ABT16500CMTD 数据手册

 浏览型号74ABT16500CMTD的Datasheet PDF文件第2页浏览型号74ABT16500CMTD的Datasheet PDF文件第3页浏览型号74ABT16500CMTD的Datasheet PDF文件第4页浏览型号74ABT16500CMTD的Datasheet PDF文件第5页浏览型号74ABT16500CMTD的Datasheet PDF文件第6页浏览型号74ABT16500CMTD的Datasheet PDF文件第7页 
April 1993  
Revised January 1999  
74ABT16500  
18-Bit Universal Bus Transceivers with 3-STATE Outputs  
plementary (OEAB is active HIGH and OEBA is active  
LOW).  
General Description  
To ensure the high-impedance state during power up or  
power down, OE should be tied to GND through a pulldown  
resistor; the minimum value of the resistor is determined by  
the current-sourcing capability of the driver.  
The ABT16500 18-bit universal bus transceiver combines  
D-type latches and D-type flip-flops to allow data flow in  
transparent, latched, and clocked modes.  
Data flow in each direction is controlled by output-enable  
(OEAB and OEBA), latch-enable (LEAB and LEBA), and  
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the  
device operates in the transparent mode when LEAB is  
HIGH. When LEAB is LOW, the A data is latched if CLKAB  
is held at a HIGH or LOW logic level. If LEAB is LOW, the A  
bus data is stored in the latch/flip-flop on the HIGH-to-LOW  
transition of CLKAB. Output-enable OEAB is active-high.  
When OEAB is HIGH, the outputs are active. When OEAB  
is LOW, the outputs are in the high-impedance state.  
Features  
■ Combines D-Type latches and D-Type flip-flops for  
operation in transparent, latched, or clocked mode  
■ Flow-through architecture optimizes PCB layout  
■ Guaranteed latch-up protection  
■ High impedance glitch free bus loading during entire  
power up and power down cycle  
■ Non-destructive hot insertion capability  
Data flow for B to A is similar to that of A to B but uses  
OEBA, LEBA, and CLKBA. The output enables are com-  
Ordering Code:  
Order Number  
74ABT16500CSSC  
74ABT16500CMTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.  
Connection Diagram  
Function Table (Note 1)  
Inputs  
Output  
Pin Assignment for SSOP  
OEAB  
LEAB CLKAB  
A
X
L
B
L
X
H
H
L
X
X
X
↓
Z
H
H
H
H
H
H
L
H
L
H
L
L
↓
H
X
X
H
L
H
L
B0 (Note 2)  
B0 (Note 3)  
L
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,  
LEBA, and CLKBA.  
Note 2: Output level before the indicated steady-state input conditions  
were established.  
Note 3: Output level before the indicated steady-state input conditions  
were established, provided that CLKAB was LOW before LEAB went LOW.  
© 1999 Fairchild Semiconductor Corporation  
DS011581.prf  
www.fairchildsemi.com  
1234567...9

中文翻译

下载PDF

与74ABT16500CMTD相关器件

型号 品牌 获取价格 描述 数据表
74ABT16500CMTDX FAIRCHILD

获取价格

 		18-Bit Bus Transceiver
74ABT16500CSSC FAIRCHILD

获取价格

 		18-Bit Universal Bus Transceivers with 3-STATE Outputs
74ABT16500CSSCX FAIRCHILD

获取价格

 		18-Bit Bus Transceiver
74ABT16501 FAIRCHILD

获取价格

 		18-Bit Universal Bus Transceivers with 3-STATE Outputs
74ABT16501A NXP

获取价格

 		18-bit universal bus transceiver 3-State
74ABT16501ADG NXP

获取价格

 		IC ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.10 MM, PLASTIC, MO-15
74ABT16501ADGG NXP

获取价格

 		18-bit universal bus transceiver 3-State
74ABT16501ADGG-T NXP

获取价格

 		IC ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP2-56, Bus
74ABT16501ADG-T NXP

获取价格

 		IC ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Transceiver
74ABT16501ADL NXP

获取价格

 		18-bit universal bus transceiver 3-State

与74ABT16500CMTD相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证