生命周期: | Obsolete | 包装说明: | DIP, |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.38 | 系列: | LS |
JESD-30 代码: | R-PDIP-T14 | 逻辑集成电路类型: | J-K FLIP-FLOP |
位数: | 2 | 功能数量: | 2 |
端子数量: | 14 | 最高工作温度: | 70 °C |
最低工作温度: | 输出极性: | COMPLEMENTARY | |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | DIP |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
传播延迟(tpd): | 30 ns | 认证状态: | Not Qualified |
最大供电电压 (Vsup): | 5.25 V | 最小供电电压 (Vsup): | 4.75 V |
标称供电电压 (Vsup): | 5 V | 表面贴装: | NO |
技术: | TTL | 温度等级: | COMMERCIAL |
端子形式: | THROUGH-HOLE | 端子位置: | DUAL |
触发器类型: | NEGATIVE EDGE | 最小 fmax: | 30 MHz |
Base Number Matches: | 1 |
型号 | 品牌 | 描述 | 获取价格 | 数据表 |
74LS73A | FAIRCHILD | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outp |
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74LS73A | NXP | IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, FF |
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74LS73A | HITACHI | Dual J-K Flip-Flops(with Clear) |
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74LS73A | TI | DUAL J-K FLIP-FLOPS WITH CLEAR |
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74LS73F | NXP | IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, FF |
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74LS73FC | FAIRCHILD | J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDFP14, |
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74LS73FCQM | FAIRCHILD | J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDFP14, |
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74LS73FCQR | FAIRCHILD | J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, CDFP14, |
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74LS73N | NXP | IC LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, PL |
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74LS73NA+1 | RAYTHEON | J-K Flip-Flop, 2-Func, Negative Edge Triggered, TTL, PDIP14, |
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